APPENDICES
Item
Output device
Watch data
ON region setting
Output enable/disable bit
Forced output bit
Table 4.8 Other devices list (Continued)
Q173DCPU/Q172DCPU
M0 to M8191
U \G10000.0 to U \G(10000 + p –1).F
W0 to W1FFF
Absolute value address
U \G10000 to U \G(10000 + p –1)
W0 to W1FFF
Constant (Hn/Kn)
U \G10000 to U \G(10000 + p – 1)
M0 to M8191
SM0 to SM1999
U \G10000.0 to U \G(10000 + p – 1).F
(Note-2) : "p" indicates the user setting area points of Multiple CPU high speed transmission area in each CPU.
(Note-3) : Setting range varies depending on the setting units.
POINT
Refer to Chapter 2 for number of user setting area points of Multiple CPU high
speed transmission area.
X0 to X1FFF
Y0 to Y1FFF
—
B0 to B1FFF
(Note-2)
D0 to D8191
#0 to #7999
(Note-2)
D0 to D8191
#0 to #7999
(Note-3)
(Note-2)
X0 to X1FFF
Y0 to Y1FFF
—
B0 to B1FFF
F0 to F2047
(Note-2)
APP - 34
Q173HCPU/Q172HCPU
X0 to X1FFF
Y0 to Y1FFF
M0 to M8191
L0 to L8191
B0 to B1FFF
—
D0 to D8191
W0 to W1FFF
#0 to #8191
Absolute value address
—
D0 to D8191
W0 to W1FFF
#0 to #8191
(Note-3)
Constant (Hn/Kn)
—
X0 to X1FFF
Y0 to Y1FFF
M0 to M8191
L0 to L8191
B0 to B1FFF
F0 to F2047
M9000 to M9255
—