Upp_Wd2 Voltage/Clock Frequency Adjusting; Power Distribution, Control And Reset; Power-Up Sequence (Reset Mode) - Nokia RH-47 Series Description

Hide thumbs Also See for RH-47 Series:

Table of Contents

Nokia Customer Care

In SLEEP mode, the VCXO is off. UEM generates low frequency clock signal (32.768 kHz)

that is fed to UPP_WD2, Bluetooth and ZOCUS.

UPP_WD2 voltage/clock frequency adjusting

No external clock is available for UPP_WD2 before VCXO starts. As reset is released, the

VCXO is running and MCU uses the 26 MHz clock while DSP is in reset. There are three

identical DPLL's, for MCU, for DSP and for accessory interfaces which can be controlled

independently. The clock for MCU can be up to 104 MHz and 117 MHz is the maximum

clock frequency for the DSP. These clock signals are used either directly (SDRAM IF) or

divided down for the interfaces (for example, flash IF).

All power (except backup battery power) is drawn from the BL-6C Li-Ion battery located

in the B-cover. Current flows through ZOCUS current sense the resistor which is used for

current measurement by ZOCUS and thus for remaining operating time estimation.

1CK board contains one power ASIC, UEM and discrete regulators needed for generating

the different operating voltages. The discrete regulators consist of a step-down DC-DC

converter to power UPPWD2 voltage core and a step-up DC-DC converter for display

module backlighting. The keyboard backlighting is powered with a discrete driver.

RESET mode can be entered in four ways: by inserting the battery or charger, by RTC

alarm or by pressing the power key. The VCXO is powered by the UEM. After a 220 ms

delay, regulators are configured and UEM enters the PWR_ON mode and system reset

PURX is released.

During system start-up, in the RESET state, the regulators are enabled, and each regula-

Issue 1 05/04

Company Confidential

6 - Baseband Description and Troubleshooting

Figure 2: RH-47 Clocking.

Company Confidential

RH-47

Page 11

Table of Contents