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Mitsubishi Electric FX5 User Manual page 216

Melsec iq-f series
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Receive only
When data are received from the counterpart device, the process completes when the received data matches the receive
packet and the receiving process is performed. For verification mismatch, the receive data is discarded, and the CPU unit
waits for the next receive data. (Page 216 Operation Image and Data Structure of Predefined Protocol)
Settable receive packet (expected packet) is up to 16.
FX5 CPU module
Receive packet
(expected packet)
Data area (2)
Receiving
completed
The operation is as follows.
■Normal completion
FX5 CPU module
Drive S(P).CPRTCL
instruction
Completion device (d)
Completion status
indication device (d)+1
Counterpart device
■Error completion (transmission monitoring timeout error)
FX5 CPU module
Drive S(P).CPRTCL
instruction
Completion device (d)
Completion status
indication device (d)+1
Counterpart device
• When variables are included in receive packet elements, variable parts are not verified.
• When more than one receive packet is specified, received data is verified with the receive packet
information of the first registered packet in the order of registration. The receive processing is performed
once received data match one of the receive packet number, and further verification is not performed.
• The receive packet number which is matched as the result of the verification is stored in the control data of
the S(P).CPRTCL instruction.
APPENDIX
214
Appendix 2 Operation Image and Data Structure of Predefined Protocol
Verification
mismatch
Header
Data area (1)
Verification
match
Header
Data area (2)
Receive wait time
Receive packet
Counterpart
device
Receive packet
Verification match
Receive packet
Error occurred
Verification
mismatch
Receive packet

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