Mitsubishi Electric FX5 User Manual page 385
Melsec iq-f series
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- Programming manual (1112 pages) ,
- User manual (958 pages) ,
- Reference manual (44 pages)
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No.
Name
SD8496
Default gateway IP address setting [Low-order]
SD8497
Default gateway IP address setting [High-order]
SD8498
IP address storage area write error code
SD8499
IP address storage area clear error code
Serial communication
The special registers for serial communication are shown below.
R: Read only, R/W: Read/Write
No.
Name
SD8500
Serial communication error code (ch1)
SD8501
Serial communication error details (ch1)
SD8502
Serial communication setting (ch1)
SD8503
Serial communication operational mode (ch1)
SD8510
Serial communication error code (ch2)
SD8511
Serial communication error details (ch2)
SD8512
Serial communication setting (ch2)
SD8513
Serial communication operational mode (ch2)
SD8520
Serial communication error code (ch3)
SD8521
Serial communication error details (ch3)
SD8522
Serial communication setting (ch3)
SD8523
Serial communication operational mode (ch3)
SD8530
Serial communication error code (ch4)
SD8531
Serial communication error details (ch4)
SD8532
Serial communication setting (ch4)
SD8533
Serial communication operational mode (ch4)
SD8560
Remaining points of send data (ch1)
SD8561
Receive data points monitor (ch1)
SD8563
Receive sum (received data) (ch1)
SD8564
Receive sum (received result) (ch1)
SD8565
Send sum (ch1)
SD8570
Remaining points of send data (ch2)
SD8571
Receive data points monitor (ch2)
SD8573
Receive sum (received data) (ch2)
SD8574
Receive sum (received result) (ch2)
SD8575
Send sum (ch2)
SD8580
Remaining points of send data (ch3)
SD8581
Receive data points monitor (ch3)
SD8583
Receive sum (received data) (ch3)
SD8584
Receive sum (received result) (ch3)
SD8585
Send sum (ch3)
SD8590
Remaining points of send data (ch4)
SD8591
Receive data points monitor (ch4)
SD8593
Receive sum (received data) (ch4)
SD8594
Receive sum (received result) (ch4)
SD8595
Send sum (ch4)
SD8621
Timeout time (ch1)
SD8622
8-bit processing mode (ch1)
SD8623
Header 1 and 2 (ch1)
Description
This register stores the default gateway IP address.
This register stores error codes if writing to IP address storage
area is failed.
This register stores error codes if clear to IP address storage area
is failed.
Description
This register stores the serial communication error code 1 (ch1).
This register stores the serial communication error details 1 (ch1).
This register stores the serial communication setting (ch1).
This register stores the serial communication operational mode 1
(ch1).
This register stores the serial communication error code 2 (ch2).
This register stores the serial communication error details 2 (ch2).
This register stores the serial communication setting (ch2).
This register stores the serial communication operational mode 2
(ch2).
This register stores the serial communication error code 3 (ch3).
This register stores the serial communication error details 3 (ch3).
This register stores the serial communication setting (ch3).
This register stores the serial communication operational mode 3
(ch3).
This register stores the serial communication error code 4 (ch4).
This register stores the serial communication error details 4 (ch4).
This register stores the serial communication setting (ch4).
This register stores the serial communication operational mode 4
(ch4).
This register stores the remaining points of send data (ch1).
This register stores the receive data points monitor (ch1).
This register stores the receive sum (received data) (ch1).
This register stores the receive sum (received result) (ch1).
This register stores the send sum (ch1).
This register stores the remaining points of send data (ch2).
This register stores the receive data points monitor (ch2).
This register stores the receive sum (received data) (ch2).
This register stores the receive sum (received result) (ch2).
This register stores the send sum (ch2).
This register stores the remaining points of send data (ch3).
This register stores the receive data points monitor (ch3).
This register stores the receive sum (received data) (ch3).
This register stores the receive sum (received result) (ch3).
This register stores the send sum (ch3).
This register stores the remaining points of send data (ch4).
This register stores the receive data points monitor (ch4).
This register stores the receive sum (received data) (ch4).
This register stores the receive sum (received result) (ch4).
This register stores the send sum (ch4).
This register stores the timeout time (ch1).
This register stores the 8-bit processing mode (ch1).
This register stores the header 1 and 2 (ch1).
R/W
R/W
R
R
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
APPX
Appendix 2 Special Register List
A
383
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