Interrupt priority setting
The interrupt priority (1 to 3) of interruptions from modules can be changed.
Navigation window [Parameter] [FX5UCPU] [CPU Parameter] "Interrupt Settings" "Interrupt Priority Setting
from Module"
Operating procedure
"Interrupt Settings" window
"Detailed Setting" window
Displayed items
Item
Multiple Interrupt
Interrupt Priority
Detailed Setting
*1 The lower the numerical value, the higher the interrupt priority.
Disabling/enabling interrupts with a specified or lower priority
Interrupts with a priority equal or lower than that specified by the DI or EI instruction can be disabled or enabled even when
multiple interrupts are present.
For details, refer to MELSEC iQ-F FX5 Programming Manual (Instructions, Standard Functions/Function Blocks).
Disabled interrupt priorities and the current interrupt priority can be checked in SD758 (Interrupt disabling for
each priority setting value) and SD757 (Current interrupt priority) respectively.
1.
2.
Description
Sets whether or not to enable multiple interrupt.
Sets the priority of the interrupt pointers I0 to I31.
Set Multiple Interrupt to "Enable" on the "Interrupt
Settings" window, and click "Detailed Setting".
Change the priority of each interrupt pointer.
Setting range
• Disable
• Enable
*1
1 to 3
9 INTERRUPT FUNCTION
9.1 Multiple Interrupt Function
9
Default
Disable
2
65