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Mitsubishi Electric MELSEC iQ-F FX5 User Manual page 144

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I/O signals
This section stores the I/O signals for the CPU module.
Address
6700H(26368) to 6703H(26371)
■List of I/O signals
The following table lists I/O signals.
Classification
Input signals
Output signals
Do not use (turn on) any "use prohibited" signals as an input or output signal to the CPU module.
Doing so may cause malfunction of the programmable controller system.
■Module failure (Un\G26368 b0)
This signal indicates whether the module is normal or faulty.
Off: Module normal
On: Module failure
Module failure
(Un\G26368 b0)
Module ready
(Un\G26368 b15)
■Own station data link status (Un\G26368 b1)
This signal indicates the data link status of the own station.
'Operation status of own station' (SB006E) has the same functionality. Use either of 'Data link status of own station'
(Un\G26368 b1) or 'Operation status of own station' (SB006E) for programming.
Note that the on/off conditions of 'Data link status of own station' (Un\G26368 b1) are the opposite to those of 'Operation
status of own station' (SB006E). The conditions of the data link status of own station (b1) are as follows:
Off: Data link stop
On: Data link in progress
■Data link status of other stations (Un\G26368 b3)
This signal indicates the data link status of other stations (remote station, intelligent device station) when using the master
station.
'Data link status of other stations' (SB0080) uses the same signal. Use either of 'Data link status of other station' (Un\G26368
b3) or 'Data link status of other station' (SB0080) for programming.
Off: All stations normal
On: Faulty station found (The status of the faulty station is stored in 'Data link status of other stations' (SW0080, SW0081).)
It takes maximum of six seconds for 'Data link status of other stations' (Un\G26368 b3) to turn on after a slave
station connected to the master station becomes faulty. The time until this signal turns on differs depending on
the system configuration and error status.
APPX
142
Appendix 4 Buffer Memory
Description
This section stores the input and output signals for the CPU module.
Address
Bit
6700H (26368)
b0
b1
b2
b3
b4 to b14
b15
6701H (26369)
b0 to b15
6702H (26370)
b0 to b15
6703H (26371)
b0 to b15
Signal name
Module failure
Own station data link status
Use prohibited
Data link status of other stations (only master station)
Use prohibited
Module ready
Use prohibited
Use prohibited
Use prohibited
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