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■NZ2GN2S-D41PD02
Item
Reset control
External reset ON/OFF
part setting
Timing control
Data sampling timing
part setting
Filter sampling pulse
Data update timing
Logging cycle timing
Digital input
Input filter upper limit
control part
value X0 to Input filter
setting
upper limit value XF
Digital output
Output signal selection
control part
Y0 to Output signal
*3
setting
selection YF
Differential output
HOLD/CLEAR Y0 to
Differential output
HOLD/CLEAR Y7
Description
Sets ON/OFF of the reset issued to the
board when FPGA control is stopped.
Sets the sampling timing (cycle) for DC
input and differential (RS-422/RS-485)
input.
Sets the operation cycle of the digital
filter.
For the DC I/O board, this setting is
fixed to the data sampling timing.
The data sampling timing cannot be set
for the differential I/O board. The same
value as this setting is set for the data
sampling timing.
Sets the output timing (cycle) for DC
output and differential (RS-422/RS-
485) output.
*1
Sets the logging cycle.
Sets the filter upper limit value of the
digital filter for DC input and differential
*2
(RS-422) input.
Sets the signal to be output to the DC
output and differential (RS-422) output.
■B0 terminal block, B1 terminal block
It is masked and cannot be set.
■B2 terminal block
*4
Sets the differential (RS-422) output
value when FPGA control is stopped
for a differential I/O board.
Setting range
• ON
• OFF
■B0 terminal block, B1 terminal block
0.10s to 655.36s (set in units of 0.01s)
■B2 terminal block
0.01s to 655.36s (set in units of 0.01s)
■B0 terminal block, B1 terminal block
Data sampling timing (fixed)
■B2 terminal block
• 0.01s
• 0.02s
• 0.04s
• 0.08s
• 0.10s
• 0.14s
• 0.16s
• 0.20s
• 0.32s
• 0.40s
• 0.50s
• 1.00s
• 2.00s
• 10.00s
• 100.00s
■B0 terminal block, B1 terminal block
0.10s to 655.36s (set in units of 0.01s)
■B2 terminal block
0.01s to 655.36s (set in units of 0.01s)
1s to 32768s (set in units of 1s)
0 to 4095
• Register setting value (RY)
• User circuit output
■B0 terminal block, B1 terminal block
It is masked and cannot be set.
■B2 terminal block
• CLEAR (fixed to L)
• CLEAR (fixed to H)
• HOLD
8 FPGA MODULE CONFIGURATION TOOL
8.6 Parameter Setting Function
Default
ON
■B0 terminal block, B1
terminal block
0.15s
■B2 terminal block
0.01s
■B0 terminal block, B1
terminal block
Data sampling timing
■B2 terminal block
0.01s
■B0 terminal block, B1
terminal block
0.10s
8
■B2 terminal block
0.01s
1s
■B0 terminal block, B1
terminal block
4000
■B2 terminal block
1500
Register setting value
(RY)
CLEAR (fixed to H)
103
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