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Verification item
Verification items for the provided patterns are shown below. Check the reference for details on the validation patterns.
Validation pattern
Item
name
FNA_TOP_01010101
DC input/output
check
FNA_TOP_01010102
Differential input/
output check
FNA_TOP_01010103
Pulse output
check
FNA_TOP_01010104
Counter
operation check
FNA_TOP_01010105
Logging (non-
time division
mode) check
FNA_TOP_01010106
Analog output
check
FNA_TOP_01010107
Analog input and
logging (time
division mode)
check
FNA_TOP_01010108
Logging
(automatic
transfer mode)
check
Verification item
■Purpose
To perform inversion control and output control for the DC input of DC input/output circuit
boards, and to check that it is output as the DC output of the DC input/output circuit
boards
■Check item
Perform inversion control and output control for the DC input of DC input/output circuit
boards, and check that it is output as the DC output of the DC input/output circuit boards.
(Check the above for each of circuit boards B0, B1, B2, E0, E1, and E2.)
■Purpose
To perform inversion control and output control for the differential input of differential input/
output circuit boards, and to check that it is output to the differential output of the
differential input/output circuit boards
■Check item
Perform inversion control and output control for the differential input of differential input/
output circuit boards, and check that it is output to the differential output of the differential
input/output circuit boards. (Check the above for each of circuit boards B0, B1, B2, E0,
E1, and E2.)
■Purpose
To check that the pulse output of the user circuit block is output to the differential output of
differential input/output circuit boards
■Check item
Check the operation of the pulse output of the user circuit block. (B0, B1, B2, E0, E1, and
E2 connect to differential input/output circuit boards.)
■Purpose
To check that 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-phase
multiple of 1) implemented in the user circuit block count against differential inputs from
differential input/output circuit boards
■Check item
Check the operation of 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-
phase multiple of 1) in the user circuit block. (B0, B1, B2, E0, E1, and E2 connect to
differential input/output circuit boards.)
■Purpose
To check that the differential input of differential input/output circuit boards is logged to
DDR3L SDRAM
■Check item
Perform logging for the differential input of differential input/output circuit boards and 32-
bit ring counters (2-phase multiple of 4), and check that data is logged to DDR3L SDRAM.
Logging is performed in trigger operation mode. (B0, B1, B2, E0, E1, and E2 connect to
differential input/output circuit boards.)
■Purpose
To check that analog outputs (analog data, enable, LDAC) are performed according to the
register settings of the user circuit block
■Check item
Check that analog outputs (analog data, enable, LDAC) are performed according to the
register settings of the user circuit block. (B0, B1, and B2 do not connect, while E0, E1,
and E2 connect to analog input/output circuit boards.)
■Purpose
To check that the analog input of analog input/output circuit boards is logged to DDR3L
SDRAM
■Check item
Check that the analog input of analog input/output circuit boards is logged to DDR3L
SDRAM in a time division manner. Logging is performed in trigger operation mode. (B0,
B1, and B2 do not connect, while E0, E1, and E2 connect to analog input/output circuit
boards.)
■Purpose
To check that logging can be performed normally when b0 of Logging control part
automatic transfer mode setting (usr_wreg_095) (FPGA register address: 1000_B12AH)
is set to Enable (1)
■Check item
Check that, when b0 of Logging control part automatic transfer mode setting
(usr_wreg_095) (FPGA register address: 1000_B12AH) is set to Enable (1), the logging
enable signal (logging start) is output according to the logging control trigger and that data
is written to DDR3L SDRAM normally.
Reference
Page 150 DC input/
output check
Page 152
Differential input/
output check
Page 154 Pulse
output check
Page 157 Counter
operation check
Page 162 Logging
(non-time division
mode) check
Page 165 Analog
output check
Page 166 Analog
input and logging
(time division mode)
check
Page 168 Logging
(automatic transfer
mode) check
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
149
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