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DC input/output check
■Validation pattern name
FNA_TOP_01010101
■Purpose
To perform inversion control and output control for the DC input of DC input/output circuit boards, and to check that it is output
as the DC output of the DC input/output circuit boards
■Check item
Perform inversion control and output control for the DC input of DC input/output circuit boards, and check that it is output as
the DC output of the DC input/output circuit boards. (Check the above for each of circuit boards B0, B1, B2, E0, E1, and E2)
■Procedure
Configuration: B0 to B2 DC input/output circuit boards and E0 to E2 DC input/output circuit boards, without verification model
connection of DDR3L SDRAM
1.
Reset the sequence. (Set Initialization completed signal (init_done) to 1.)
2.
Set the register areas for B0 to B2 DC input/output circuit boards and E0 to E2 DC input/output circuit boards. Also, set
the related register areas as shown in the table below.
Register name
Filter sampling pulse (B0) (tim_iob0x_samp)
Filter sampling pulse (B1) (tim_iob1x_samp)
Filter sampling pulse (B2) (tim_iob2x_samp)
Filter sampling pulse (E0) (tim_ioe0x_samp)
Filter sampling pulse (E1) (tim_ioe1x_samp)
Filter sampling pulse (E2) (tim_ioe2x_samp)
Data sampling timing (B0) (tim_iob0x_en)
Data sampling timing (B1) (tim_iob1x_en)
Data sampling timing (B2) (tim_iob2x_en)
Data sampling timing (E0) (tim_ioe0x_en)
Data sampling timing (E1) (tim_ioe1x_en)
Data sampling timing (E2) (tim_ioe2x_en)
Data update timing (B0) (tim_iob0x_conv)
Data update timing (B1) (tim_iob1x_conv)
Data update timing (B2) (tim_iob2x_conv)
Data update timing (E0) (tim_ioe0x_conv)
Data update timing (E1) (tim_ioe1x_conv)
Data update timing (E2) (tim_ioe2x_conv)
Input filter upper limit value (IOB0_X0) (B0) (iport_iob0_0_filcnt_upper) to Input filter upper limit value
(IOB0_XF) (B0) (iport_iob0_f_filcnt_upper)
Input filter upper limit value (IOB1_X0) (B1) (iport_iob1_0_filcnt_upper) to Input filter upper limit value
(IOB1_XF) (B1) (iport_iob1_f_filcnt_upper)
Input filter upper limit value (IOB2_X0) (B2) (iport_iob2_0_filcnt_upper) to Input filter upper limit value
(IOB2_XF) (B2) (iport_iob2_f_filcnt_upper)
Input filter upper limit value (IOE0_X0) (E0) (iport_ioe0_0_filcnt_upper) to Input filter upper limit value
(IOE0_XF) (E0) (iport_ioe0_f_filcnt_upper)
Input filter upper limit value (IOE1_X0) (E1) (iport_ioe1_0_filcnt_upper) to Input filter upper limit value
(IOE1_XF) (E1) (iport_ioe1_f_filcnt_upper)
Input filter upper limit value (IOE2_X0) (E2) (iport_ioe2_0_filcnt_upper) to Input filter upper limit value
(IOE2_XF) (E2) (iport_ioe2_f_filcnt_upper)
3.
Perform the preprocessing of internal operation start.
10 FPGA DEVELOPMENT
150
10.3 FPGA Verification Procedure
Setting
Reference
value
0000H
Page 523 Filter sampling pulse
0000H
0000H
0000H
0000H
0000H
0009H
Page 524 Data sampling timing (B)
0013H
001DH
0009H
Page 525 Data sampling timing (E)
0013H
001DH
0009H
Page 526 Data update timing
0013H
001DH
0009H
0013H
001DH
0000H
Page 528 Input filter counter upper
limit
0000H
0000H
0000H
0000H
0000H
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