Table of Contents
Advertisement
Differential input/output check
■Validation pattern name
FNA_TOP_01010102
■Purpose
To perform inversion control and output control for the differential input of differential input/output circuit boards, and to check
that it is output to the differential output of the differential input/output circuit boards
■Check item
Perform inversion control and output control for the differential input of differential input/output circuit boards, and check that it
is output to the differential output of the differential input/output circuit boards. (Check the above for each of circuit boards B0,
B1, B2, E0, E1, and E2)
■Procedure
Configuration: B0 to B2 differential input/output circuit boards and E0 to E2 differential input/output circuit boards, without
verification model connection of DDR3L SDRAM
1.
Reset the sequence.
2.
Set the register areas for B0 to B2 differential input/output circuit boards and E0 to E2 differential input/output circuit
boards. Also, set the related register areas as shown in the table below.
Register name
Filter sampling pulse (B0) (tim_iob0x_samp)
Filter sampling pulse (B1) (tim_iob1x_samp)
Filter sampling pulse (B2) (tim_iob2x_samp)
Filter sampling pulse (E0) (tim_ioe0x_samp)
Filter sampling pulse (E1) (tim_ioe1x_samp)
Filter sampling pulse (E2) (tim_ioe2x_samp)
Data update timing (B0) (tim_iob0x_conv)
Data update timing (B1) (tim_iob1x_conv)
Data update timing (B2) (tim_iob2x_conv)
Data update timing (E0) (tim_ioe0x_conv)
Data update timing (E1) (tim_ioe1x_conv)
Data update timing (E2) (tim_ioe2x_conv)
Input filter upper limit value (IOB0_X0) (B0) (iport_iob0_0_filcnt_upper) to Input filter upper limit value
(IOB0_XF) (B0) (iport_iob0_f_filcnt_upper)
Input filter upper limit value (IOB1_X0) (B1) (iport_iob1_0_filcnt_upper) to Input filter upper limit value
(IOB1_XF) (B1) (iport_iob1_f_filcnt_upper)
Input filter upper limit value (IOB2_X0) (B2) (iport_iob2_0_filcnt_upper) to Input filter upper limit value
(IOB2_XF) (B2) (iport_iob2_f_filcnt_upper)
Input filter upper limit value (IOE0_X0) (E0) (iport_ioe0_0_filcnt_upper) to Input filter upper limit value
(IOE0_XF) (E0) (iport_ioe0_f_filcnt_upper)
Input filter upper limit value (IOE1_X0) (E1) (iport_ioe1_0_filcnt_upper) to Input filter upper limit value
(IOE1_XF) (E1) (iport_ioe1_f_filcnt_upper)
Input filter upper limit value (IOE2_X0) (E2) (iport_ioe2_0_filcnt_upper) to Input filter upper limit value
(IOE2_XF) (E2) (iport_ioe2_f_filcnt_upper)
3.
Perform the preprocessing of internal operation start.
10 FPGA DEVELOPMENT
152
10.3 FPGA Verification Procedure
Setting
Reference
value
0000H
Page 523 Filter sampling pulse
0000H
0000H
0000H
0000H
0000H
0000H
Page 526 Data update timing
0000H
0000H
0000H
0000H
0000H
0000H
Page 528 Input filter counter upper
limit
0000H
0000H
0000H
0000H
0000H
Advertisement
Table of Contents
Troubleshooting
