Table of Contents
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Register name
Pulse output part pulse width upper limit value (lower side) (B0) (usr_wreg_110)
Pulse output part pulse width upper limit value (upper side) (B0) (usr_wreg_111)
Pulse output part pulse width upper limit value (lower side) (B1) (usr_wreg_115)
Pulse output part pulse width upper limit value (upper side) (B1) (usr_wreg_116)
Pulse output part pulse width upper limit value (lower side) (B2) (usr_wreg_11A)
Pulse output part pulse width upper limit value (upper side) (B2) (usr_wreg_11B)
Pulse output part pulse width upper limit value (lower side) (E0) (usr_wreg_11F)
Pulse output part pulse width upper limit value (upper side) (E0) (usr_wreg_120)
Pulse output part pulse width upper limit value (lower side) (E1) (usr_wreg_124)
Pulse output part pulse width upper limit value (upper side) (E1) (usr_wreg_125)
Pulse output part pulse width upper limit value (lower side) (E2) (usr_wreg_129)
Pulse output part pulse width upper limit value (upper side) (E2) (usr_wreg_12A)
Pulse output part output pulse count upper limit value (lower side) (B0) (usr_wreg_112)
Pulse output part output pulse count upper limit value (upper side) (B0) (usr_wreg_113)
Pulse output part output pulse count upper limit value (lower side) (B1) (usr_wreg_117)
Pulse output part output pulse count upper limit value (upper side) (B1) (usr_wreg_118)
Pulse output part output pulse count upper limit value (lower side) (B2) (usr_wreg_11C)
Pulse output part output pulse count upper limit value (upper side) (B2) (usr_wreg_11D)
Pulse output part output pulse count upper limit value (lower side) (E0) (usr_wreg_121)
Pulse output part output pulse count upper limit value (upper side) (E0) (usr_wreg_122)
Pulse output part output pulse count upper limit value (lower side) (E1) (usr_wreg_126)
Pulse output part output pulse count upper limit value (upper side) (E1) (usr_wreg_127)
Pulse output part output pulse count upper limit value (lower side) (E2) (usr_wreg_12B)
Pulse output part output pulse count upper limit value (upper side) (E2) (usr_wreg_12C)
Pulse output part pulse output enable (B0) (usr_wreg_1B8)
Pulse output part pulse output enable (B1) (usr_wreg_1B9)
Pulse output part pulse output enable (B2) (usr_wreg_1BA)
Pulse output part pulse output enable (E0) (usr_wreg_1BB)
Pulse output part pulse output enable (E1) (usr_wreg_1BC)
Pulse output part pulse output enable (E2) (usr_wreg_1BD)
Pulse output part pulse output selection 0 (B0) (usr_wreg_130)
Pulse output part pulse output selection 1 (B0) (usr_wreg_131)
Pulse output part pulse output selection 2 (B0) (usr_wreg_132)
Pulse output part pulse output selection 0 (B1) (usr_wreg_133)
Pulse output part pulse output selection 1 (B1) (usr_wreg_134)
Pulse output part pulse output selection 2 (B1) (usr_wreg_135)
Pulse output part pulse output selection 0 (B2) (usr_wreg_136)
Pulse output part pulse output selection 1 (B2) (usr_wreg_137)
Pulse output part pulse output selection 2 (B2) (usr_wreg_138)
Pulse output part pulse output selection 0 (E0) (usr_wreg_139)
Pulse output part pulse output selection 1 (E0) (usr_wreg_13A)
Pulse output part pulse output selection 2 (E0) (usr_wreg_13B)
Pulse output part pulse output selection 0 (E1) (usr_wreg_13C)
Pulse output part pulse output selection 1 (E1) (usr_wreg_13D)
Pulse output part pulse output selection 2 (E1) (usr_wreg_13E)
Pulse output part pulse output selection 0 (E2) (usr_wreg_13F)
Pulse output part pulse output selection 1 (E2) (usr_wreg_140)
Pulse output part pulse output selection 2 (E2) (usr_wreg_141)
Setting
Reference
value
0003H
Page 587 Pulse output part pulse
width upper limit value
0000H
0003H
0000H
0003H
0000H
0003H
0000H
0003H
0000H
0003H
0000H
0064H
Page 588 Pulse output part output
pulse count upper limit value
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0001H
Page 597 Pulse output part pulse
output enable
0001H
0001H
0001H
0001H
0001H
E4E4H
Page 589 Pulse output part pulse
output selection
E4E4H
0000H
E4E4H
E4E4H
0000H
E4E4H
E4E4H
0000H
E4E4H
E4E4H
0000H
E4E4H
E4E4H
0000H
E4E4H
E4E4H
0000H
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
155
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Troubleshooting
