Table of Contents
Advertisement
Counter operation check
■Validation pattern name
FNA_TOP_01010104
■Purpose
To check that 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-phase multiple of 1) implemented in the user
circuit block count against differential inputs from differential input/output circuit boards
■Check item
Check the operation of 32-bit ring counters (2-phase multiple of 4)/32-bit ring counters (1-phase multiple of 1) in the user
circuit block. (Circuit boards B0, B1, B2, E0, E1, and E2 connect to differential input/output circuit boards.)
■Procedure
Configuration: B0 to B2 differential input/output circuit boards and E0 to E2 differential input/output circuit boards, without
verification model connection of DDR3L SDRAM
1.
Reset the sequence.
2.
Set the register areas as shown in the table below.
Register name
Filter sampling pulse (B0) (tim_iob0x_samp)
Filter sampling pulse (B1) (tim_iob1x_samp)
Filter sampling pulse (B2) (tim_iob2x_samp)
Filter sampling pulse (E0) (tim_ioe0x_samp)
Filter sampling pulse (E1) (tim_ioe1x_samp)
Filter sampling pulse (E2) (tim_ioe2x_samp)
Data sampling timing (B0) (tim_iob0x_en)
Data sampling timing (B1) (tim_iob1x_en)
Data sampling timing (B2) (tim_iob2x_en)
Data sampling timing (E0) (tim_ioe0x_en)
Data sampling timing (E1) (tim_ioe1x_en)
Data sampling timing (E2) (tim_ioe2x_en)
Input filter upper limit value (IOB0_X0) (B0) (iport_iob0_0_filcnt_upper) to Input filter upper limit value
(IOB0_X7) (B0) (iport_iob0_7_filcnt_upper)
Input filter upper limit value (IOB1_X0) (B1) (iport_iob1_0_filcnt_upper) to Input filter upper limit value
(IOB1_X7) (B1) (iport_iob1_7_filcnt_upper)
Input filter upper limit value (IOB2_X0) (B2) (iport_iob2_0_filcnt_upper) to Input filter upper limit value
(IOB2_X7) (B2) (iport_iob2_7_filcnt_upper)
Input filter upper limit value (IOE0_X0) (E0) (iport_ioe0_0_filcnt_upper) to Input filter upper limit value
(IOE0_X7) (E0) (iport_ioe0_7_filcnt_upper)
Input filter upper limit value (IOE1_X0) (E1) (iport_ioe1_0_filcnt_upper) to Input filter upper limit value
(IOE1_X7) (E1) (iport_ioe1_7_filcnt_upper)
Input filter upper limit value (IOE2_X0) (E2) (iport_ioe2_0_filcnt_upper) to Input filter upper limit value
(IOE2_X7) (E2) (iport_ioe2_7_filcnt_upper)
Input filter upper limit value (IOB0_DIO485_I) (B0) (iport_iob0_dio485_filcnt_upper)
Input filter upper limit value (IOB1_DIO485_I) (B1) (iport_iob1_dio485_filcnt_upper)
Input filter upper limit value (IOB2_DIO485_I) (B2) (iport_iob2_dio485_filcnt_upper)
Input filter upper limit value (IOE0_DIO485_I) (E0) (iport_ioe0_dio485_filcnt_upper)
Input filter upper limit value (IOE1_DIO485_I) (E1) (iport_ioe1_dio485_filcnt_upper)
Input filter upper limit value (IOE2_DIO485_I) (E2) (iport_ioe2_dio485_filcnt_upper)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B0) (usr_wreg_188)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B1) (usr_wreg_18B)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (B2) (usr_wreg_18E)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E0) (usr_wreg_191)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E1) (usr_wreg_194)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction (E2) (usr_wreg_197)
Setting
Reference
value
0000H
Page 523 Filter sampling pulse
0000H
0000H
0000H
0000H
0000H
0000H
Page 524 Data sampling timing (B)
0000H
0000H
0000H
Page 525 Data sampling timing (E)
0000H
0000H
0000H
Page 528 Input filter counter upper
limit
0000H
0000H
0000H
0000H
0000H
0000H
Page 534 Input filter counter upper
limit
0000H
0000H
0000H
0000H
0000H
0000H
Page 593 Counter control part 32-bit
ring counter (2-phase multiple of 4)
0000H
preset instruction
0000H
0000H
0000H
0000H
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
157
Advertisement
Table of Contents
Troubleshooting
