Table of Contents
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Register name
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B0)
(usr_wreg_189)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (B0)
(usr_wreg_18A)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B1)
(usr_wreg_18C)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (B1)
(usr_wreg_18D)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (B2)
(usr_wreg_18F)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (B2)
(usr_wreg_190)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (E0)
(usr_wreg_192)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (E0)
(usr_wreg_193)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (E1)
(usr_wreg_195)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (E1)
(usr_wreg_196)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower side) (E2)
(usr_wreg_198)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper side) (E2)
(usr_wreg_199)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(B0) (usr_wreg_0A3)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(B0) (usr_wreg_0A4)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(B1) (usr_wreg_0AB)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(B1) (usr_wreg_0AC)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(B2) (usr_wreg_0B3)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(B2) (usr_wreg_0B4)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(E0) (usr_wreg_0BB)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(E0) (usr_wreg_0BC)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(E1) (usr_wreg_0C3)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(E1) (usr_wreg_0C4)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (lower side)
(E2) (usr_wreg_0CB)
Counter control part 32-bit ring counter (2-phase multiple of 4) counter upper limit value (upper side)
(E2) (usr_wreg_0CC)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0)
(usr_wreg_0A5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B1)
(usr_wreg_0AD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B2)
(usr_wreg_0B5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E0)
(usr_wreg_0BD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E1)
(usr_wreg_0C5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E2)
(usr_wreg_0CD)
10 FPGA DEVELOPMENT
158
10.3 FPGA Verification Procedure
Setting
Reference
value
0000H
Page 594 Counter control part 32-bit
ring counter (2-phase multiple of 4)
preset data
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0064H
Page 583 Counter control part 32-bit
ring counter (2-phase multiple of 4)
counter upper limit value
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0064H
0000H
0201H
Page 584 Counter control part 32-bit
ring counter (2-phase multiple of 4)
input signal selection
0201H
0201H
0201H
0201H
0201H
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