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11.
Set b9 of Write/read data control register (usr_wrdat_ctrl) (FPGA register address: 1000_A000H) to 1.
12.
Read Counter control part 32-bit ring counter (2-phase multiple of 4) counter value (lower side) (B0) (usr_rreg_1B3)
(FPGA register address: 1000_BB66H) to Counter control part 32-bit ring counter (2-phase multiple of 4) counter value
(upper side) (E2) (usr_rreg_1BE) (FPGA register address: 1000_BB7CH) and Counter control part 32-bit ring counter (1-
phase multiple of 1) counter value (lower side) (B0) (usr_rreg_1BF) (FPGA register address: 1000_BB7EH) and Counter
control part 32-bit ring counter (1-phase multiple of 1) counter value (lower side) (E2) (usr_rreg_1CA) (FPGA register
address: 1000_BB94H). Check that the counter value (corresponds to 4 for 2-phase multiple of 4 and 1 (+ preset) for 1-
phase multiple of 1.
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
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Troubleshooting
