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Register name
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0)
(usr_wreg_0A5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B1)
(usr_wreg_0AD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B2)
(usr_wreg_0B5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E0)
(usr_wreg_0BD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E1)
(usr_wreg_0C5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E2)
(usr_wreg_0CD)
3.
After the preprocessing of the internal operation start, start the internal operation.
When the internal operation is set to Stop, IOB0-2_RSTL/IOE_RSTL becomes 0. When it is set to Start, IOB0-2_RSTL/
IOE_RSTL becomes 1. Also, exp_IO[B|E][0-2]_Y[0-7] and exp_IO[B|E][0-2]_YCK1 become to 0.
4.
Set b0 of Logging operation control register (lgdw_ctrl) (FPGA register: 1000_9000H) to 1, and start write logging. Input
differential signals while logging. Refer to the table and chart below for input values.
Terminal name
IOB0_X[0]
IOB0_X[1]
IOB0_X[2]
IOB0_X[3]
IOB0_X[4]
IOB0_X[5]
IOB0_X[6]
IOB0_X[7]
IOB1_X[0]
IOB1_X[1]
IOB1_X[2]
IOB1_X[3]
IOB1_X[4]
IOB1_X[5]
IOB1_X[6]
IOB1_X[7]
IOB2_X[0]
IOB2_X[1]
IOB2_X[2]
IOB2_X[3]
IOB2_X[4]
IOB2_X[5]
IOB2_X[6]
IOB2_X[7]
Setting value
Refer to the following chart.
Refer to the following chart.
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Refer to the following chart.
Refer to the following chart.
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Refer to the following chart.
Refer to the following chart.
0000H
0000H
Setting
value
0201H
0403H
0605H
0807H
0502H
0308H
Terminal name
IOE0_X[0]
IOE0_X[1]
IOE0_X[2]
IOE0_X[3]
IOE0_X[4]
IOE0_X[5]
IOE0_X[6]
IOE0_X[7]
IOE1_X[0]
IOE1_X[1]
IOE1_X[2]
IOE1_X[3]
IOE1_X[4]
IOE1_X[5]
IOE1_X[6]
IOE1_X[7]
IOE2_X[0]
IOE2_X[1]
IOE2_X[2]
IOE2_X[3]
IOE2_X[4]
IOE2_X[5]
IOE2_X[6]
IOE2_X[7]
10.3 FPGA Verification Procedure
Reference
Page 584 Counter control part 32-bit
ring counter (2-phase multiple of 4)
input signal selection
Setting value
0000H
0000H
0000H
0000H
0000H
0000H
Refer to the following chart.
Refer to the following chart.
0000H
Refer to the following chart.
0000H
0000H
Refer to the following chart.
0000H
0000H
0000H
0000H
0000H
Refer to the following chart.
0000H
0000H
0000H
0000H
Refer to the following chart.
10 FPGA DEVELOPMENT
10
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Troubleshooting
