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Analog input and logging (time division mode) check
■Validation pattern name
FNA_TOP_01010107
■Purpose
To check that the analog input of analog input/output circuit boards is logged to DDR3L SDRAM
■Check item
Check that the analog input of analog input/output circuit boards is logged to DDR3L SDRAM in a time division manner.
Logging is performed in trigger operation mode. (B0, B1, and B2 do not connect, while E0, E1, and E2 connect to analog
input/output circuit boards.)
■Procedure
Use a configuration in which B0 to B2 do not connect and E0 to E2 connect to analog input/output circuit boards, with the
DDR3L SDRAM verification model connected.
1.
Reset the sequence.
2.
Set the register areas for E0 to E2 analog input/output circuit boards, and set the related register areas as shown in the
table below. After register setting, set b1 of Write/read data control register (usr_wrdat_ctrl) (FPGA register address:
1000_A000H) to 1.
Register name
Logging operation control register (lgdw_ctrl)
Logging data size setting (lgdw_area)
Set number of sampling after trigger (lower side)
(lgdw_triggered_lsample)
Set number of sampling after trigger (upper side)
(lgdw_triggered_usample)
Logging cycle timing (tim_log_cyc)
Data sampling timing (E0) (tim_ioe0x_en)
Data sampling timing (E1) (tim_ioe1x_en)
Data sampling timing (E2) (tim_ioe2x_en)
Select A/D conversion timing (aiport_ad_cyc_sel)
User circuit logging mode selection (usr_logmode_sel)
Logging control part end trigger signal selection (usr_wreg_092)
Logging control part sampling pulse signal selection (usr_wreg_093)
3.
After the preprocessing of the internal operation start, start the internal operation.
When the internal operation is set to Stop, IOB0-2_RSTL/IOE_RSTL becomes 0. When the internal operation is set to Start,
IOB0-2_RSTL/IOE_RSTL becomes 1.
4.
Set E0, E1, and E2 to change from Conversion-disable to Conversion-enable.
Check that E0, E1, and E2 ADCs are initialized when the settings are changed.
5.
After ADC initialization processing is completed, set b0 of Logging operation control register (lgdw_ctrl) (FPGA register
address: 1000_9000H) to 1, and start logging.
Input any value from the ADC during logging.
6.
After 8s has elapsed, set b1 of Logging control part user logging control (usr_wreg_180) (FPGA register address:
1000_B300H) to 1, and b1 of Write/read data control register (usr_wrdat_ctrl) (FPGA register address: 1000_A000H) to
1, and input the end trigger.
B1 of Logging control part user logging control (usr_wreg_180) (FPGA register address: 1000_B300H) has a rising edge
detection circuit, so b1 must be set to 0 after set to 1.
10 FPGA DEVELOPMENT
166
10.3 FPGA Verification Procedure
Setting value
Reference
3100H
Page 550 Logging operation control register
0002H
Page 553 Logging data size setting
0080H
Page 555 Set number of sampling after trigger
0000H
0003H
Page 527 Logging cycle timing
018FH
Page 525 Data sampling timing (E)
031FH
04AFH
0000H
Page 540 A/D conversion timing selection
0001H
Page 558 User circuit logging mode selection
0015H
Page 580 Logging control part end trigger signal selection
0015H
Page 581 Logging control part sampling pulse signal selection
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Troubleshooting
