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Register name
Logging control part sampling pulse signal selection (usr_wreg_093)
Logging control part automatic transfer mode setting (usr_wreg_095)
3.
After the preprocessing of the internal operation start, start the internal operation.
When the internal operation is set to Stop, IOB0-2_RSTL/IOE_RSTL becomes 0. When the internal operation is set to Start,
IOB0-2_RSTL/IOE_RSTL becomes 1. Also, exp_IO[B|E][0-2]_Y[0-7] and exp_IO[B|E][0-2]_YCK1 become 0.
4.
Input 1 to IOB0_X0 and set b3 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) to
1.
5.
Input a value in the order of 0, 1, 0 to IOB0_X1.
6.
Input 0 to IOB0_X0 and set b3 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) to
0.
Logging system flag (lgdw_sys_sts) (FPGA register address: 1000_9004H), and Constant read register 14 (usr_alwreg_0E)
(FPGA register address: 1000_A04CH) are initialized by writing each bit of Flag clear register (lgdw_flag_clr) (FPGA register
address: 1000_9006H), and Constant write register 14 (usr_alwreg_0E) with 1. After checking the status of each register, the
initialization is performed by writing each bit of Flag clear register (lgdw_flag_clr) and Constant write register 14
(usr_alwreg_0E) (FPGA register address: 1000_A02CH) with 1.
After setting b3 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) to 0, check that the
register areas have the value shown in the table below.
Register name
b8 of Logging state register (lgdw_sts)
b13 of Logging system flags (lgdw_sys_sts)
b14 of Logging system flags (lgdw_sys_sts)
b0 of Constant read register 14 (usr_alwreg_0E)
b1 of Constant read register 14 (usr_alwreg_0E)
7.
After setting b3 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) to 1, input 1 to
IOB0_X0.
8.
Input a value in the order of 0, 1, 0 to IOB0_X1. (1clk pulse)
9.
Wait until b8 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) becomes 1.
10.
Set b3 of Logging operation control register (lgdw_ctrl) (FPGA register address: 1000_9000H) to 0 and input 0 to
IOB0_X0.
After inputting 0 to IOB0_X0, check that the register areas have the value shown in the table below.
Register name
b8 of Logging state register (lgdw_sts)
b13 of Logging system flags (lgdw_sys_sts)
b14 of Logging system flags (lgdw_sys_sts)
b15 of Logging system flags (lgdw_sys_sts)
b0 of Constant read register 14 (usr_alwreg_0E)
b1 of Constant read register 14 (usr_alwreg_0E)
Setting
Reference
value
0002H
Page 581 Logging control part sampling pulse signal
selection
0001H
Page 582 Logging control part automatic transfer mode
setting
Expected value
0
0
1
Expected value
1
0
1
0
10.3 FPGA Verification Procedure
Reference
Page 551 Logging state register
Page 552 Logging system flag
Page 571 Always read register 14
Reference
Page 551 Logging state register
Page 552 Logging system flag
Page 571 Always read register 14
10 FPGA DEVELOPMENT
10
169
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Table of Contents
Troubleshooting
