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■Reset target list
The reset target list is shown below.
Reset cause
Reset (RSTL)
• Initializing at power-on
• Configurating
Internal operation start/stop
• FPGA control start request (RY0): start
• FPGA control stop request (RY1): stop
For details, refer to the following.
Page 315 FPGA Control Function
WDT error
Clock control part (cc2_top)
PLL is used to generate system clock (clk100m). Other than IP, it operates with the system clock.
TOP part (top1)
CLKIN_SYS
Reset control part
(rc2_top)
■Clock list
Clock signal
Function
clk100m
System clock
*1 Input signals to the user circuit block are synchronized with the system clock and input.
Reset function
Sets all FPGA register areas until the FPGA circuit is established.
Shows the processing content of each block as below when internal operation start/stop is stop.
■Timing generator
Resets the internal circuit and is fixed at 0 without outputting pulses to the circuit in the level immediately
below.
■Digital input control part
Resets the internal circuit and fixes the output to the circuit in the level immediately below to 0.
■Digital output control part
Holds (HOLD) or clears (CLEAR) the value that was output until just before. ( Page 315 FPGA
Control Function)
■Digital input/output control part
• Input side: Same as digital input control part
• Output side: Same as digital output control part
• I/O direction setting signal: Not applicable
■Analog input control part
Stops A/D conversion. If it stops during conversion processing, the A/D conversion value is discarded.
■Analog output control part
Stops D/A conversion. If it stops during conversion processing, it will stop after D/A conversion end.
■User circuit block
Resets the internal circuit and outputs an inactive signal (0) to the circuit in the level immediately below. (It
will be processed in the sample circuit. If the RTL is modified, the behavior will change.)
The watchdog timer (WDT) monitors and detects hardware failure.
A WDT error occurs when access to the FPGA from the MCU is interrupted for a long time due to a
hardware failure.
When a WDT error occurs, the value that was output immediately before is held (HOLD) or cleared
(CLEAR) in the same way as when FPGA control stops. For details, refer to the following.
Page 315 FPGA Control Function
If the MCU can detect a WDT error, a hardware error (error code: 3C00H) is generated, and a reset is
issued from the MCU to the FPGA. (WDT errors may not be detected due to hardware failures that occur.)
Clock control part
(cc2_top)
refclk
PLL
rst_hw_n
rst
Frequency
Origin
100MHz
FPGA internal PLL
System clock
clk100m
outclk_0
locked
Where to use
• Timing generator
• Microcomputer I/F part
• Logging part
• Digital/analog input/output function block input/output
selector
• Platform part
*1
• User circuit block
11 FPGA INTERNAL CIRCUIT
All FFs
PLL_LOCK
189
11.3 Standard Circuit
11
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Table of Contents
Troubleshooting
