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■Timing chart
Logging starts when the internal operation start/stop is Start and the logging start signal (logging start (register part), signal
with logging enable selected) is Start (1). After logging starts, when the logging cycle timing (logging cycle timing, signal with
user sampling pulse selected) is enabled (1), the DDR3L SDRAM address is generated and the logging data and time
information are written to the DDR3L SDRAM.
Logging cycle timing pulse
tg_log_tmgpulse_x_clk100m_1shot_reg
Automatic transfer mode (logging part)
re_rs_lgdw_ctrl_10_clk100m_reg
Logging control trigger
re_rs_lgdw_ctrl_3_clk100m_reg
Internal operation start/stop register
re_rd_mode_ctrl2_clk100m_reg
Logging start (register part)
re_rs_lgdw_ctrl_1_clk100m_reg
Time information
Logging data
uc_logdat_clk100m_reg
DDR3L SDRAM address
DDR3L SDRAM write processing
■Automatic transfer mode
In this mode, the firmware uses the logging control trigger to notify the FPGA of the period during which logging is possible,
and operates according to the notification content. If the content of the notification is not followed, the logging operation
(logging in progress, or when logging stops) will be maintained and will continue.
Logging start (register part)
Logging cycle timing pulse
tg_log_tmgpulse_x_clk100m_1shot_reg
Internal operation start/stop register
re_rd_mode_ctrl2_clk100m_reg
Automatic transfer mode (logging part)
re_rs_lgdw_ctrl_10_clk100m_reg
Logging control trigger
re_rs_lgdw_ctrl_3_clk100m_reg
Logging control start violation error
lf_logctrl_uperr_clk100m_1shot_reg
Logging control stop violation error
lf_logctrl_downerr_clk100m_1shot_reg
(1) Minor error
(2) Automatic transfer mode (logging part) = Enable && Logging control trigger = Rising edge enable, so logging starts
(3) Automatic transfer mode (logging part) = Enable && Logging control trigger = Falling edge enable, so logging stops.
(4) Automatic transfer mode (logging part) = Enable && Logging control trigger = Falling edge enable, so logging does not start.
State transitions and conditions of logging during automatic transfer mode are shown below.
• Automatic transfer mode (logging part): Enable
• Internal operation start/stop register: Start
Logging
Logging start
control
(register part)
trigger
Rising edge
During rising edge
enable
During rising edge
When L
When L
Falling edge
During rising edge
enable
During rising edge
When L
When L
Others
*1 Writing from FPGA to DDR3L-SDRAM
*2 No access from FPGA to DDR3L-SDRAM
*3 Only when the logging start (register part) is falling edge, a logging control stop violation error is output.
11 FPGA INTERNAL CIRCUIT
192
11.3 Standard Circuit
(I)
L
(I)
Disable
(I)
Falling edge enable
Falling edge enable
(I)
Start
Stop
(I)
Logging stop
Logging start
(Internal)
(I)
Logging data M
(Internal)
(O)
DDR3L SDRAM write processing (logging data M, address N)
(I)
Logging stop
Logging start
(I)
L
(I)
Stop
Start
(I)
Disable
Enable
Falling edge
enable
(I)
Rising edge enable
(I)
(I)
Logging
in progress
(2)
Current state
During logging
Logging stop
During logging
Logging stop
During logging
Logging stop
During logging
Logging stop
Logging cycle timing pulse (minimum 1μs)
Time information
Logging data M + 1
Logging data M + 2
Address N
Logging stop
Logging start
Falling edge enable
Falling edge enable
(1)
Logging stop
(3)
(4)
Next state
*1
During logging
*2
During logging
*1
During logging
*2
Logging stop
*1
During logging
*2
Logging stop
*1
Logging stop
*2
Logging stop
Hold previous state
Logging data M + 3
Address N + 1
DDR3L SDRAM write processing (logging data M + 2, address N + 1)
Logging stop
Logging start
Logging stop
Rising edge enable
Rising edge enable
(1)
Logging
Logging
in progress
in progress
(5)
(6)
Logging control
start violation error
None
None
None
None
Minor error
Minor error
None
None
None
Logging start
Logging stop
Falling edge enable
Falling edge enable
(1)
Logging stop
(7)
Logging control
stop violation error
None
None
*3
Minor error
*3
Minor error
None
None
None
None
None
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Troubleshooting
