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Register part (re2_top)
This block notifies the setting values inside the FPGA via the platform part from the MCU.
Top part (top1)
Bus
Microcom-
Platform part
connection
(pt2_top)
puter
■Function List
Item
Notification of setting values to user circuit block
Loading status information from user circuit block
Notification of setting values to each block
Loading status information of each block
■Connection and setting value notification timing
The connection between the register part and the user circuit block, and the setting value notification timing are shown below.
FPGA address
Register name
1000_A000H
usr_wrdat_ctrl
1000_A002H
usr_logmode_sel
1000_A004H
usr_micon_syserr
1000_0010H to
usr_alwreg_00 to
1000_A02FH
usr_alwreg_0F
1000_A030H to
usr_alrreg_00 to usr_alrreg_0F
1000_A04FH
1000_B000H to
usr_wreg_000 to
1000_B2FFH
usr_wreg_17F
1000_B300H to
usr_wreg_180 to
1000_B3FFH
usr_wreg_1FF
1000_B800H to
usr_rreg_000 to usr_rreg_17F
1000_BAFFH
1000_BB00H to
usr_rreg_180 to usr_rreg_1FF
1000_BBFFH
User circuit register control area
Bus
Always write register write data
Register part
connection
(transient area)
(re2_top)
Writing data (cyclic area)
Constant read register
Read data (cyclic area)
Read data (transient area)
Various setting values
Various statuses
Operation
Notifies the user circuit block of the setting values (user circuit register control area, constant
write area, write data (transient area), write data (cyclic area)) from the MCU.
Notifies the MCU of the status in the user circuit block (constant read area, read data (cyclic
area), read data (transient area)).
Notifies each block of the setting value notified from the MCU.
Notifies the MCU of the status in each block.
Register
User circuit signal name
overview
Write/read data
No connection
control register
User circuit logging
re_rs_usr_logmode_sel_1_0_clk100
mode selection
m_reg
MCU system error
re_rd_usr_micon_syserr_clk100m_re
notification
g
Always write register
re_rs_usr_alwreg_00_clk100m_reg
to
re_rs_usr_alwreg_00_clk100m_reg
Always read register
uc_rs_usr_alrreg_00_clk100m_reg to
uc_rs_usr_alrreg_0f_clk100m_reg
Write data (transient
re_rs_usr_wreg_000_clk100m_reg to
area)
re_rs_usr_wreg_17f_clk100m_reg
Writing data (cyclic
re_rs_usr_wreg_180_clk100m_reg to
area)
re_rs_usr_wreg_1ff_clk100m_reg
Read data (transient
uc_rs_usr_rreg_000_clk100m_reg to
area)
uc_rs_usr_rreg_17f_clk100m_reg
Read data (cyclic
uc_rs_usr_rreg_180_clk100m_reg to
area)
uc_rs_usr_rreg_1ff_clk100m_reg
User circuit part
(uc2_top)
Various blocks
Setting value
notification timing
Constant notification
Constant notification
Constant notification
Constant notification
When 1 is set to Write/read
data control register [0]
When 1 is set to Write/read
data control register [1]
When 1 is set to Write/read
data control register [8]
When 1 is set to Write/read
data control register [9]
11 FPGA INTERNAL CIRCUIT
11.3 Standard Circuit
11
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Troubleshooting
