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■Timing chart
The selection of the timing pulse of the digital filter differs between the DC input/output circuit board and the differential input/
output circuit board.
The DC input/output circuit board performs digital filtering in synchronization with the data sampling timing.
The differential input/output circuit board sets the filter sampling pulse, generates the timing pulse, and implements the digital
filter. The timing chart of the digital input control part is shown below.
• DC input/output circuit board
Filter sampling pulse setting register: FH
clk100m
[Timing generator]
Data sampling timing
tg_sampling_tmgpulse_x_clk100m_1shot_reg
[Digital input control part]
DC input output enable [0]
IOB/Ex_XOEL[0]
DC input output enable [1]
IOB/Ex_XOEL[1]
Digital input signal [7:0]
IOB/Ex_X[7:0]
Data enable (lower)
det_en_l
Data enable (upper)
dat_en_u
Digital input signal (lower)
ioxx_x[7:0]
Digital input signal (upper)
ioxx_x[15:8]
Filter enable (lower)
fil_en[7:0]
Filter enable (upper)
fil_en[15:8]
1
12-bit up/down counter*
Digital input signal (after filtering)*
di_ioxx_x_clk100m_reg[0]
(1) After match comparison, output in one level of FF.
*1 1 bit is indicated. [15:1] has the same process.
• Differential input/output circuit board
Filter sampling pulse setting register: Other than FH
clk100m
[Timing generator]
Data sampling pulse
tg_sampling_tmgpulse_0_clk100m_1shot_reg
Filter sampling pulse
tg_fil_tmgpulse_0_clk100m_1shot_reg
[Digital input control part]
DC input output enable [0]
IOB/Ex_XOEL[0]
DC input output enable [1]
IOB/Ex_XOEL[1]
Digital input signal [7:0]
IOB/Ex_X[7:0]
Data enable (lower)
dat_en_l
Data enable (upper)
dat_en_u
Digital input signal (lower)
ioxx_x[7:0]
Digital input signal (upper)
ioxx_x[15:8]
1
12-bit up/down counter*
Digital input signal (after filtering)*
di_ioxx_x_clk100m_reg[0]
(1) After match comparison, output in one level of FF.
*1 1 bit is indicated.
11 FPGA INTERNAL CIRCUIT
198
11.3 Standard Circuit
(I)
(O)
(External terminal output)
(External terminal output)
(External terminal input)
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
1
(O)
(I)
(O)
L
(O) L
(External terminal output)
H
(External terminal output)
H
(External terminal input)
Differential input 0
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
1
(O)
L
L
H
H
L
Differential
Differential
input 0
input 0
(1)
0.1μs
DC input (lower)
DC input (upper)
DC input (lower)
Digital filter processing
(1)
0.1μs
Differential
Differential
Differential input 1
input 2
input 2
Differential
Differential
input 2
input 2
Digital filter processing
DC input (upper)
Digital filter processing
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