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■Operation
The analog input control part performs the ADC register settings, ADC register initialization and ADC register setting end, and
A/D conversion processing that reads A/D conversion values from the ADC. ADC register initialization and ADC register
setting end set register areas in the ADC when the internal operation start/stop is Start and A/D conversion enable/disable
setting is set to Enable (1). For A/D conversion processing, by setting the A/D conversion start to Start(1), the A/D conversion
value is read from the ADC in synchronization with the data sampling pulses that are input at constant cycle from the timing
generator. Both current and voltage A/D conversion values are input from the ADC, and A/D conversion values set by the
ADC range setting (aiport_ade0_0-3_range to aiport_ade2_8-b_range) are output to the user circuit block. The analog input
control part outputs the 12-bit A/D conversion values (ai_ioe0_aival_0_clk100m_reg to ai_ioe0_aival_b_clk100m_reg) to the
user circuit block at the same time as the A/D conversion value enable (ai_io_aival_vald_clk100m_reg). The A/D conversion
value connected to the FPGA is a 16-bit 2's complement.
• ADC register initialization, ADC register end
(I)
Internal operation start/stop register
(I)
A/D conversion enable/disable setting
IOE0_X0
(External terminal output)
(IOE0_CSL[0])
IOE0_X2
(External terminal output)
(IOE0_AD_SCLK)
IOE0_X4
(External terminal output)
(IOE0_AD_SDI)
IOE0_XOEL0
(External terminal input)
(IOE0_AD0_DOUTA)
• A/D conversion processing
Data sampling pulse
(Internal)
[Analog input control part]
IOE0_X0
(IOE0_CONVST)
(External terminal output)
IOE0_X7
(IOE0_AD_BUSY)
(External terminal input)
IOE0_X1
(IOE0_AD_CSL[0])
(External terminal output)
IOE0_XOEL0
(IOE0_AD0_DOUTA)
(External terminal input)
IOE0_XOEL1
(IOE0_AD0_DOUTB)
(External terminal input)
IOE0_X3
IOE0_AD_CSL[1]
(External terminal output)
IOE0_YCK0
(IOE0_AD1_DOUTA)
(External terminal input)
IOE0_YCK1
(IOE0_AD1_DOUTB)
(External terminal input)
IOE0_X5
IOE0_AD_CSL[2]
(External terminal output)
IOE0_Y0
(IOE0_AD2_DOUTA)
(External terminal input)
IOE0_Y1
(IOE0_AD2_DOUTB)
(External terminal input)
A/D conversion value enable
ai_io_aival_vald_clk100m_reg
(O)
A/D conversion value 0 (E0)
(O)
ai_ioe0_aival_0_clk100m_reg
A/D conversion value 1 (E0)
ai_ioe0_aival_1_clk100m_reg
(O)
·
A/D conversion value b (E0)
ai_ioe0_aival_b_clk100m_reg
(O)
L
L
H
H
1
2
3
4
/WEN
R/W ADD5 ADD4 ADD3
L
④
CH3 current input
②
CH1 current input
⑧
CH7 current input
⑥
CH5 current input
⑫
CHB current input
⑩
CH9 current input
5
6
7
8
9
10
ADD2
ADD1
ADD0
DIN7
DIN6
4μs
CH3 voltage input
CH2 current input
CH1 voltage input
CH0 current input
CH7 voltage input
CH6 current input
CH5 voltage input
CH4 current input
CHB voltage input
CHA current input
CH9 voltage input
CH8 current input
11
12
13
14
15
16
DIN5
DIN4
DIN3
DIN2
DIN0
DIN0
DATA OUT
③
CH2 voltage input
①
CH0 voltage input
⑦
CH6 voltage input
⑤
CH4 voltage input
⑪
CHA voltage input
⑨
CH8 voltage input
①
②
⑫
11 FPGA INTERNAL CIRCUIT
11.3 Standard Circuit
11
207
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Troubleshooting
