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■Operation
The analog output control part performs D/A conversion processing to transfer the D/A conversion value to the DAC.
The analog output control part register setting is performed by firmware. After analog output control part register setting end,
follow the analog output control register ("Select D/A conversion value" (aoport_da_data_sel), "Select D/A conversion timing"
(aoport_da_cyc_sel), and "Select DAC LDAC signal" (aoport_da_ldac_sel)) to transfer the D/A conversion values CH0 to
CH1 (E0 to E2) to the DAC in synchronization with the data update timing that is input at constant cycle from the timing
generator. The timing chart for D/A conversion processing is shown below.
Data update timing
(I)
D/A conversion value CH0 (E0...E2)
(I)
D/A conversion value CH1 (E0...E2)
(I)
IOE0...2_Y4
(External terminal output)
(IOE0...2_DA_SYNCL)
IOE0...2_Y2
(External terminal output)
(IOE0...2_DA_SCLK)
IOE0...2_Y3
(External terminal output)
(IOE0...2_DA_SDI)
IOE0...2_Y6
(External terminal output)
(IOE0...2_DA_LDACL[0])
IOE0...2_Y7
(External terminal output)
(IOE0...2_DA_LDACL[1])
■Correspondence between D/A conversion values and analog output values
The DAC connected to this FPGA outputs 16-bit offset binary when setting the voltage, and 16-bit straight binary when setting
the current. The table below shows the correspondence between D/A conversion values and analog output values.
• Specifications for current output (0.2 to 19.8mA)
D/A conversion value
64880
64879
657
656
655
• Voltage output specification (-9.9 to 9.9V)
D/A conversion value
65207
65206
330
329
328
■Configurable functions
The function that can be set is shown below.
• Offset function
Transmission of D/A conversion value CH0 (E0...E2)
L
D/A conversion value CH0
D/A conversion value CH1
H
H
D31
D30
D29
D28
L
L
Analog output value (typical)
19.79980469mA
19.79949951mA
0.200500488mA
0.200195313mA
0.199890137mA
Analog output value (typical)
9.899597168V
9.899291992V
-9.899291992V
-9.899597168V
-9.899902344
Transmission of D/A conversion value CH1 (E0...E2)
Data update timing (fastest 6μs)
D2
D1
D0
D31
Analog output value
(maximum)
19.85920410mA
19.85889801mA
0.20110199mA
0.20079590mA
0.200489807mA
Analog output value
(maximum)
9.919396362V
9.919090576V
-9.919090576V
-9.919396362V
-9.919702148V
11 FPGA INTERNAL CIRCUIT
D30
D29
D0
Analog output value
(minimum)
19.74040527mA
19.74010101mA
0.199898987mA
0.199594727mA
0.199290466mA
Analog output value
(minimum)
9.879797974V
9.879493408V
-9.879493408V
-9.879797974V
-9.880102539V
11.3 Standard Circuit
11
213
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Troubleshooting
