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■Offset function
Offset errors caused by external factors of DAC can be compensated by the DAC offset value for each channel.
DAC offset channel (E)(remote buffer memory address: 0601H, 0605H, 0609H, 060DH, 0611H, 0615H), setting it can
automatically add or subtract up to 32768 resolutions for each channel.
The resolution for the DAC output voltage range is shown below.
DAC output current/voltage range
-9.9 to 9.9V
0.2 to 19.8mA
The formula for calculating the analog output value is shown below.
• Analog output value = Resolution (Digital input for D/A conversion + DAC offset value)
The DAC offset value is the offset binary (initial value: 8000H) set by DAC offset CH (E)(remote buffer memory address:
0601H, 0605H, 0609H, 060DH, 0611H, 0615H).
Set the digital input for D/A conversion + DAC offset value within the following range.
• If the DAC range setting CH (E)(remote buffer memory address: 0602H, 0606H, 060AH, 060EH,
0612H, 0616H) setting is 9.9V
328 Digital input for D/A conversion + DAC offset value 65207
• If the DAC range setting CH (E)(remote buffer memory address: 0602H, 0606H, 060AH, 060EH,
0612H, 0616H) setting is 0.2 to 19.8mA
655 Digital input for D/A conversion + DAC offset value 64880
■DAC offset value
DAC offset channel (E)(remote buffer memory address: 0601H, 0605H, 0609H, 060DH, 0611H, 0615H), the DAC offset
values corresponding to the values set in it are shown below.
DAC offset channel (E)(remote buffer memory address: 0601H,
0605H, 0609H, 060DH, 0611H, 0615H)
0000H
0001H
8000H
8001H
FFFFH
Ex.
If the DAC range setting CH (E)(remote buffer memory address: 0602H, 0606H, 060AH, 060EH, 0612H, 0616H) is an
offset of 9.9V and 9mV, the DAC offset CH (E)(remote buffer memory address: 0601H, 0605H, 0609H, 060DH, 0611H,
0615H) is set to 7FE2H.
• Set 8000H-001EH(9mV=305V-30)=7FE2H
11 FPGA INTERNAL CIRCUIT
214
11.3 Standard Circuit
Resolution
305V
0.305A
DAC offset value (setting value from FPGA Module
Configuration Tool)
-32768
-32767
0
1
32767
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Troubleshooting
