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• Automatic transfer mode (faulty operation)
[Common to user circuit block logging part]
Logging control trigger
re_rs_lgdw_ctrl_3_clk100m_reg
[User circuit block]
Logging data
uc_logdat_clk100m_reg[431:0]
Logging end trigger
uc_logend_clk100m_reg
Logging start (user circuit block)
uc_logen_clk100m_reg
User sampling pulse
uc_loguserpulse_clk100m_reg
[Logging part]
DDR3L SDRAM
address generation
DDR3L SDRAM
(External terminal output)
write processing
(1) Even if Logging start (user circuit block) is enabled while the logging control trigger is Falling edge enable, logging in the logging block will not start. (A minor
error occurs.)
(2) Logging starts because Logging start (user circuit block) is enabled while the logging control trigger is rising edge enable.
(3) Even if Logging start (user circuit block) is disabled (0) while the logging control trigger is rising edge enable, logging in the logging block will not stop. (A
minor error occurs.)
(4) Logging stops because the logging control trigger is Falling edge enable and Logging start (user circuit block) is disabled.
No.
Description
1
Sets the internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to Start (1).
2
Sets Logging start (user circuit block) (uc_logen_clk100m_reg) to Enable (1), Logging control trigger (re_rs_lgdw_ctrl_3_clk100m_reg) to Rising edge
enable (1), and then User sampling pulse (uc_loguserpulse_clk100m_reg) to Enable (1b, 1 pulse output (clk100m)).
3
Raises a minor error. (Error code: 1430H)
4
Sets Logging control trigger (re_rs_lgdw_ctrl_3_clk100m_reg) to Rising edge enable (1), Logging start (user circuit block) (uc_logen_clk100m_reg) to
Enable (1), and then User sampling pulse (uc_loguserpulse_clk100m_reg) to Enable (1b, 1 pulse output (clk100m)).
5
Writes one record (data with time information (80 bits) and logging data (432 bits) as one unit) to DDR3L SDRAM. (One record is written for each user
sampling pulse output.)
6
Sets Logging start (user circuit block) (uc_logen_clk100m_reg) to Disable (1), Logging control trigger (re_rs_lgdw_ctrl_3_clk100m_reg) to Falling
edge enable (1), and then User sampling pulse (uc_loguserpulse_clk100m_reg) to Enable (1b, 1 pulse output (clk100m)).
7
Raises a minor error. (Error code: 1431H)
Writes one record (data with time information (80 bits) and logging data (432 bits) as one unit) to DDR3L SDRAM. (One record is written for each user
sampling pulse output.)
*Continues logging without stopping.
Register
Notifies the setting values from the MCU to the user circuit and notifies the user circuit status to the MCU. For the signal
names of the user circuit part and the register part, as well as the notification timing, refer to the following.
Page 195 Connection and setting value notification timing
11 FPGA INTERNAL CIRCUIT
224
11.4 User Circuit Block
Falling edge enable
(I)
Rising edge enable
(O)
Logging data
(O) L
(O)
L
(O)
L
(Internal)
(1)
Rising edge
Rising edge enable
enable
Logging data
Address
DDR3L SDRAM
Write processing
(2)
Falling edge enable
Rising edge enable
Logging data
Address + M
DDR3L SDRAM
Write processing
(3)
(4)
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Troubleshooting
