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■Timing chart (HOLD/CLEAR) example
clk100m
[User circuit block]
Digital output signal
uc_iob0_y_clk100m_reg[15:0]
[Digital output control part]
Data update timing
tg_dataout_tmgpulse_0_clk100m_1shot_reg
Internal operation start/stop
re_rd_mode_ctrl2_clk100m_reg
Differential output HOLD/CLEAR (B0) [1:0]
re_rs_oport_iob1y_holdclr_15_0_clk100m_reg[1:0]
Output signal selection (B0)
re_rs_oport_iob0y_osel_clk100m_reg
Output value setting register
re_rs_oport_iob0y_osel_clk100m_reg[15:0]
Digital input signal (after fetch)
sel_iob0_y_clk100m_reg[15:0]
Data selection signal
iob0_sel
Timing enable
iob0_en
Digital output signal (before output)
do_iob0_y_clk100m_reg[7:0]
Differential output
(External terminal output)
IOB0_X0...X7[7:0]
DC output output enable [0]
(External terminal output)
IOB0_YCK0
DC output output enable [1]
IOB0_YCK1
(External terminal output)
(1) Differential output HOLD/CLEAR (B0)[1:0]:
00b setting: 0 fixed output, 01b setting: 1 fixed output
10b, 11b settings: Previous value held
11 FPGA INTERNAL CIRCUIT
230
11.4 User Circuit Block
(I)
(I)
D1[15:0]
(I) L
(I)
L
(I)
CLEAR setting (00b, 01b)
(I) H
(I)
D4[15:0]
(Internal)
D1[15:0]
(Internal)
L
(Internal)
L
(O)
D1[7:0]
D1[7:0]
L
L
D2[15:0]
D5[15:0]
00H, FFH fixed output
(1)
00H, FFH fixed output
D3[15:0]
D6[15:0]
D2[15:0]
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Troubleshooting
