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■Digital control part function list
No.
Function
1
Inversion process
2
Digital output enable/disable control
■Digital control part terminal list
No.
Signal name
1
clk100m
2
usr_rst_n
3
sim_iob0_x_clk100m_reg[15:0]
4
sim_iob1_x_clk100m_reg[15:0]
5
sim_iob2_x_clk100m_reg[15:0]
6
sim_ioe0_x_clk100m_reg[15:0]
7
sim_ioe1_x_clk100m_reg[15:0]
8
sim_ioe2_x_clk100m_reg[15:0]
9
sim_iob0_dio485_i_clk100m_reg
10
sim_iob1_dio485_i_clk100m_reg
11
sim_iob2_dio485_i_clk100m_reg
12
sim_ioe0_dio485_i_clk100m_reg
13
sim_ioe1_dio485_i_clk100m_reg
14
sim_ioe2_dio485_i_clk100m_reg
15
re_rs_usr_wreg_000_clk100m_reg[1:0] to
re_rs_usr_wreg_00f_clk100m_reg[1:0]
28
re_rs_usr_wreg_014_clk100m_reg[1:0] to
re_rs_usr_wreg_023_clk100m_reg[1:0]
29
re_rs_usr_wreg_028_clk100m_reg[1:0] to
re_rs_usr_wreg_037_clk100m_reg[1:0]
30
re_rs_usr_wreg_03c_clk100m_reg[1:0] to
re_rs_usr_wreg_04b_clk100m_reg[1:0]
31
re_rs_usr_wreg_050_clk100m_reg[1:0] to
re_rs_usr_wreg_05f_clk100m_reg[1:0]
32
re_rs_usr_wreg_064_clk100m_reg[1:0] to
re_rs_usr_wreg_073_clk100m_reg[1:0]
33
re_rs_usr_wreg_080_clk100m_reg[1:0] to
re_rs_usr_wreg_085_clk100m_reg[1:0]
16
dig_iob0_y_clk100m_reg [15:0]
17
dig_iob1_y_clk100m_reg [15:0]
Overview
Inverts the digital input signal (after filtering) and outputs it to Digital output enable/disable
control. When "Digital control part enable/disable control register (IOB0_X0 B0)" [1] is set
to Enable (1), the digital input signal (after filtering) is inverted. If it is set to Disable (0),
through output occurs at Digital output enable/disable control.
Selects whether or not to output the inverted digital input signal (after filtering) to the
digital output signal (after digital control). When "Digital control part enable/disable control
register (IOB0_X0B0)" [0] is set to Enable (1), the inverted digital input signal after
inversion processing (after filtering) is directly output to the digital output signal (after
digital control). When it is set to Disable (0), 0b is output to the digital output signal (after
digital control).
I/O
Logic
Function
I
System clock
I
L
Reset for user circuit (the AND between reset and
internal operation start/stop)
I
Digital input signal (B0 after filtering)
I
Digital input signal (B1 after filtering)
I
Digital input signal (B2 after filtering)
I
Digital input signal (E0 after filtering)
I
Digital input signal (E1 after filtering)
I
Digital input signal (E2 after filtering)
I
Digital input signal (filtered digital input/output B0)
I
Digital input signal (filtered digital input/output B1)
I
Digital input signal (filtered digital input/output B2)
I
Digital input signal (filtered digital input/output E0)
I
Digital input signal (filtered digital input/output E1)
I
Digital input signal (filtered digital input/output E2)
I
Digital control part enable/disable control register
(IOB0_X0 B0) to Digital control part enable/disable
control register (IOB0_XF B0)
I
Digital control part enable/disable control register
(IOB0_X0 B1) to Digital control part enable/disable
control register (IOB0_XF B1)
I
Digital control part enable/disable control register
(IOB2_X0 B2) to Digital control part enable/disable
control register (IOB2_XF B2)
I
Digital control part enable/disable control register
(IOE0_X0 E0) to Digital control part enable/disable
control register (IOE0_XF E0)
I
Digital control part enable/disable control register
(IOE1_X0 E1) to Digital control part enable/disable
control register (IOE1_XF E1)
I
Digital control part enable/disable control register
(IOE2_X0 E2) to Digital control part enable/disable
control register (IOE2_XF E2)
I
Digital input/output control input/output control
register (B0) to Digital input/output control input/
output control register (E2)
O
Digital output signal (B0 after digital control)
O
Digital output signal (B1 after digital control)
Remarks
Connection
Initial
Pulse
destination
value
signal
cc2_top
uc2_top
0b
di2_top
0000h
di2_top
0000h
di2_top
0000h
di2_top
0000h
di2_top
0000h
di2_top
0000h
dio2_top
0b
dio2_top
0b
dio2_top
0b
dio2_top
0b
dio2_top
0b
dio2_top
0b
re2_top
All 0
re2_top
All 0
re2_top
All 0
re2_top
All 0
re2_top
All 0
re2_top
All 0
re2_top
All 0
Logging
0000h
control part,
output block
part
Logging
0000h
control part,
output block
part
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
247
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Troubleshooting
