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■Pulse output part terminal list
No.
Signal name
1
clk100m
2
usr_rst_n
3
re_rs_usr_wreg_110_clk100m_reg[15:0]
4
re_rs_usr_wreg_111_clk100m_reg[15:0]
5
re_rs_usr_wreg_112_clk100m_reg[15:0]
6
re_rs_usr_wreg_113_clk100m_reg[15:0]
7
re_rs_usr_wreg_1b8_clk100m_reg[0]
8
re_rs_usr_wreg_115_clk100m_reg[15:0]
9
re_rs_usr_wreg_116_clk100m_reg[15:0]
10
re_rs_usr_wreg_117_clk100m_reg[15:0]
11
re_rs_usr_wreg_118_clk100m_reg[15:0]
12
re_rs_usr_wreg_1b9_clk100m_reg[0]
13
re_rs_usr_wreg_11a_clk100m_reg[15:0]
14
re_rs_usr_wreg_11b_clk100m_reg[15:0]
15
re_rs_usr_wreg_11c_clk100m_reg[15:0]
16
re_rs_usr_wreg_11d_clk100m_reg[15:0]
17
re_rs_usr_wreg_1ba_clk100m_reg[0]
18
re_rs_usr_wreg_11f_clk100m_reg[15:0]
19
re_rs_usr_wreg_120_clk100m_reg[15:0]
20
re_rs_usr_wreg_121_clk100m_reg[15:0]
21
re_rs_usr_wreg_122_clk100m_reg[15:0]
22
re_rs_usr_wreg_1bb_clk100m_reg[0]
23
re_rs_usr_wreg_124_clk100m_reg[15:0]
24
re_rs_usr_wreg_125_clk100m_reg[15:0]
25
re_rs_usr_wreg_126_clk100m_reg[15:0]
26
re_rs_usr_wreg_127_clk100m_reg[15:0]
27
re_rs_usr_wreg_1bc_clk100m_reg[0]
28
re_rs_usr_wreg_129_clk100m_reg[15:0]
29
re_rs_usr_wreg_12a_clk100m_reg[15:0]
30
re_rs_usr_wreg_12b_clk100m_reg[15:0]
31
re_rs_usr_wreg_12c_clk100m_reg[15:0]
32
re_rs_usr_wreg_1bd_clk100m_reg[0]
11 FPGA INTERNAL CIRCUIT
250
11.4 User Circuit Block
I/O
Logic
Function
I
System clock
I
L
Reset for user circuit (the AND between
reset and internal operation start/stop)
I
Pulse output part pulse width upper limit
value (lower side) (B0)
I
Pulse output part pulse width upper limit
value (upper side) (B0)
I
Pulse output part output pulse count upper
limit value (lower side) (B0)
I
Pulse output part output pulse count upper
limit value (upper side) (B0)
I
Pulse output part pulse output enable (B0)
I
Pulse output part pulse width upper limit
value (lower side) (B1)
I
Pulse output part pulse width upper limit
value (upper side) (B1)
I
Pulse output part output pulse count upper
limit value (lower side) (B1)
I
Pulse output part output pulse count upper
limit value (upper side) (B1)
I
Pulse output part pulse output enable (B1)
I
Pulse output part pulse width upper limit
value (lower side) (B2)
I
Pulse output part pulse width upper limit
value (upper side) (B2)
I
Pulse output part output pulse count upper
limit value (lower side) (B2)
I
Pulse output part output pulse count upper
limit value (upper side) (B2)
I
Pulse output part pulse output enable (B2)
I
Pulse output part pulse width upper limit
value (lower side) (E0)
I
Pulse output part pulse width upper limit
value (upper side) (E0)
I
Pulse output part output pulse count upper
limit value (lower side) (E0)
I
Pulse output part output pulse count upper
limit value (upper side) (E0)
I
Pulse output part pulse output enable (E0)
I
Pulse output part pulse width upper limit
value (lower side) (E1)
I
Pulse output part pulse width upper limit
value (upper side) (E1)
I
Pulse output part output pulse count upper
limit value (lower side) (E1)
I
Pulse output part output pulse count upper
limit value (upper side) (E1)
I
Pulse output part pulse output enable (E1)
I
Pulse output part pulse width upper limit
value (lower side) (E2)
I
Pulse output part pulse width upper limit
value (upper side) (E2)
I
Pulse output part output pulse count upper
limit value (lower side) (E2)
I
Pulse output part output pulse count upper
limit value (upper side) (E2)
I
Pulse output part pulse output enable (E2)
Connection
Initial
destination
value
cc2_top
uc2_top
1b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0b
Pulse
signal
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Troubleshooting
