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■Pulse output: Pulse generation timing chart
clk100m
Pulse output part pulse output enable (B0)
re_rs_usr_wreg_1b8_clk100m_reg[15:0]
Pulse output part pulse width upper limit value
(lower side)/(upper side) (B0)
{re_rs_usr_wreg_111_clk100m_reg[15:0],
re_rs_usr_wreg_110_clk100m_reg[15:0]}
Reference counter for pulse generation
Pulse generation enable (0 degrees)
pls_0degree_en
Pulse generation enable (90 degrees)
pls_90degree_en
0 degree pulse
pls_0degree
90 degree pulse
pls_90degree
180 degree pulse
pls_180degree
270 degree pulse
pls_270degree
Pulse output part output pulse count upper limit
(lower side)/(upper side) (B0)
{re_rs_usr_wreg_113_clk100m_reg[15:0],
re_rs_usr_wreg_112_clk100m_reg[15:0]}
Number of pulse outputs (B0)
plsout_plscnt
■0-degree pulse generation, 180-degree pulse generation (same for 90-degree pulse generation
and 270-degree pulse generation)
Receives 0-degree enable from reference enable generation, inverts the output signal, and outputs it (0-degree pulse). A 180-
degree pulse is output by shifting the 0-degree pulse by one level. If "Pulse output part pulse output enable (B0)" is set to
Disable (0), the 0-degree pulse and 180-degree pulse are initialized(0) and output.
The output of the 0-degree pulse is masked by the plsen signal from the pulse output count.
■Pulse output count
It is a 32-bit linear counter that counts according to the falling edge signal of a 90 degree pulse (pls_90degree). The plsen
signal is output at 0b when the count value becomes equal to the "Pulse output part output pulse count upper limit value
(lower side)/(upper side) (B0)", and then the count-up is not performed.
If "Pulse output part pulse output enable (B0)" is Disable (0), the 32-bit linear counter is initialized (0000_0000H).
Pulse output selection
The pulse output selector selects and outputs the pulse (0-degree pulse, 90-degree pulse, 180-degree pulse, 270-degree
pulse (pls_0degree, pls_90degree, pls_180degree, pls_270degree)) to be output by each channel of each circuit board. A
block diagram of the pulse output selector is shown below.
0, 90, 180, 270 degree pulse
pls_0degree
pls_90degree
pls_180degree
pls_270degree
Pulse output part pulse output selection 0/1/2 (B0)
re_rs_usr_wreg_130_clk100m_reg[15:0]
re_rs_usr_wreg_131_clk100m_reg[15:0]
re_rs_usr_wreg_132_clk100m_reg[1:0]
Pulse output part pulse output mask 0/1 (B0)
re_rs_usr_wreg_142_clk100m_reg[15:0]
re_rs_usr_wreg_143_clk100m_reg[0]
(I)
(I)
L
(I)
(Internal)
0d
1d
2d
3d
0d
1d
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
(Internal)
(I)
(Internal)
0d
Pulse output selector (uc4_plsout_sel)
3H
2d 3d
0d
1d
2d 3d
0d
1d
2d 3d
2H
1d
00b
01b
D
Q
10b
11b
E
00b
01b
D
Q
10b
11b
E
0d
1d
2d 3d
0d
1d
2d 3d
0d
1d
No pulse output
2d
Pulse output (B0)
pls_iob0_y_clk100m_reg[0]
Pulse output (B0)
pls_iob0_y_dio485_clk100m_reg
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
255
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Troubleshooting
