Table of Contents
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Signal name
re_rs_usr_wreg_192_clk100m_reg[15:0]
re_rs_usr_wreg_193_clk100m_reg[15:0]
re_rs_usr_wreg_0bb_clk100m_reg[15:0]
re_rs_usr_wreg_0bc_clk100m_reg[15:0]
re_rs_usr_wreg_0bc_clk100m_reg [4:0]
re_rs_usr_wreg_0bc_clk100m_reg[12:8]
re_rs_usr_wreg_0bd_clk100m_reg[5]
re_rs_usr_wreg_0bd_clk100m_reg[13]
re_rs_usr_wreg_194_clk100m_reg[0]
re_rs_usr_wreg_195_clk100m_reg[15:0]
re_rs_usr_wreg_196_clk100m_reg[15:0]
re_rs_usr_wreg_0c3_clk100m_reg[15:0]
re_rs_usr_wreg_0c4_clk100m_reg[15:0]
re_rs_usr_wreg_0c5_clk100m_reg [4:0]
re_rs_usr_wreg_0c5_clk100m_reg[12:8]
re_rs_usr_wreg_0c5_clk100m_reg[5]
re_rs_usr_wreg_0c5_clk100m_reg[13]
re_rs_usr_wreg_197_clk100m_reg[0]
re_rs_usr_wreg_198_clk100m_reg[15:0]
re_rs_usr_wreg_199_clk100m_reg[15:0]
re_rs_usr_wreg_0cb_clk100m_reg[15:0]
I/O
Logic
Function
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (lower side)
(E0)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (upper side)
(E0)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(lower side) (E0)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(upper side) (E0)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E0)
Phase A input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E0)
Phase B input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E0)
Phase A register input
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E0)
Phase B register input
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset instruction (E1)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (lower side)
(E1)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (upper side)
(E1)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(lower side) (E1)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(upper side) (E1)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E1)
Phase A input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E1)
Phase B input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E1)
Phase A register input
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E1)
Phase B register input
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset instruction (E2)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (lower side)
(E2)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) preset data (upper side)
(E2)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(lower side) (E2)
Connection
Initial
Pulse
destination
value
signal
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
00h
re2_top
00h
re2_top
0b
re2_top
0b
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
00h
re2_top
00h
re2_top
0b
re2_top
0b
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
259
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Troubleshooting
