Table of Contents
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Signal name
re_rs_usr_wreg_0cc_clk100m_reg[15:0]
re_rs_usr_wreg_0cd_clk100m_reg [4:0]
re_rs_usr_wreg_0cd_clk100m_reg[12:8]
re_rs_usr_wreg_0cd_clk100m_reg[5]
re_rs_usr_wreg_0cd_clk100m_reg[13]
re_rs_usr_wreg_1a0_clk100m_reg[0]
re_rs_usr_wreg_1a1_clk100m_reg[15:0]
re_rs_usr_wreg_1a2_clk100m_reg[15:0]
re_rs_usr_wreg_0d3_clk100m_reg[15:0]
re_rs_usr_wreg_0d4_clk100m_reg[15:0]
re_rs_usr_wreg_0d5_clk100m_reg [4:0]
re_rs_usr_wreg_0d5_clk100m_reg[12:8]
re_rs_usr_wreg_0d5_clk100m_reg[5]
re_rs_usr_wreg_0d5_clk100m_reg[13]
re_rs_usr_wreg_1a3_clk100m_reg[0]
re_rs_usr_wreg_1a4_clk100m_reg[15:0]
re_rs_usr_wreg_1a5_clk100m_reg[15:0]
re_rs_usr_wreg_0db_clk100m_reg[15:0]
re_rs_usr_wreg_0dc_clk100m_reg[15:0]
re_rs_usr_wreg_0dd_clk100m_reg[4:0]
re_rs_usr_wreg_0dd_clk100m_reg[12:8]
11 FPGA INTERNAL CIRCUIT
260
11.4 User Circuit Block
I/O
Logic
Function
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) counter upper limit value
(upper side) (E2)
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E2)
Phase A input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E2)
Phase B input selection
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E2)
Phase A register input
I
Counter control part 32-bit ring counter (2-
phase multiple of 4) input signal selection (E2)
Phase B register input
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset instruction (B0)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (lower side)
(B0)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (upper side)
(B0)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(lower side) (B0)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(upper side) (B0)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B0)
Phase A input selection
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B0)
Phase Z input selection
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B0)
Phase A register input
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B0)
Phase Z register input
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset instruction (B1)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (lower side)
(B1)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) preset data (upper side)
(B1)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(lower side) (B1)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) counter upper limit value
(upper side) (B1)
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B1)
Phase A input selection
I
Counter control part 32-bit ring counter (1-
phase multiple of 1) input signal selection (B1)
Phase Z input selection
Connection
Initial
destination
value
re2_top
0000h
re2_top
00h
re2_top
00h
re2_top
0b
re2_top
0b
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
00h
re2_top
00h
re2_top
0b
re2_top
0b
re2_top
0b
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
0000h
re2_top
00h
re2_top
00h
Pulse
signal
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Table of Contents
Troubleshooting
