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Logging control part (uc3_log_top)
This module provides the logging control part with logging data (logging target data), logging enable (logging start signal),
logging end trigger (logging end pulse during trigger operation mode), and user sampling pulse (logging data sampling). The
block diagram, function list, and terminal list of the logging control part are shown below.
■Block Diagram
A/D conversion value enable (E0)
sim_ioe0_aival_vald_clk100m_reg
1
A/D conversion value CH0...CHB (E0)*
sim_ioe0_aival_0_clk100m_reg[15:0]...
sim_ioe0_aival_b_clk100m_reg[15:0]
Logging control pulse
pls_tmgpulse_log_clk100m_1shot_reg
User circuit logging mode selection
re_rs_usr_logmode_sel_1_0_clk100m_reg[0]
Logging control part logging enable signal selection
re_rs_usr_wreg_091_clk100m_reg[7:0]
Logging control part logging enable mode setting
re_rs_usr_wreg_094_clk100m_reg[0]
Logging control part 1 enable clear
re_rs_usr_wreg_181_clk100m_reg[0]
Logging control part end trigger signal selection
re_rs_usr_wreg_092_clk100m_reg[7:0]
2
32-bit ring counter (2-phase multiple of 4) (B0)*
cnt_iob0_32ring_2pha4multi_counter_clk100m_reg[31:0]
cnt_iob0_32ring_2pha4multi_pha,
cnt_iob0_32ring_2pha4multi_phb
Digital input signal (B0...E2 after filtering)
sim_ioe2_x_clk100m_reg[15:0]...
sim_iob0_x_clk100m_reg[15:0]
Digital output signal (B0 after digital control)
dig_iob0_y_clk100m_reg[9:0]
Logging control part user logging control
re_rs_usr_wreg_180_clk100m_reg[1:0]
Logging control part user sampling pulse selection
re_rs_usr_wreg_093_clk100m_reg[6:0]
Logging control trigger
re_rs_lgdw_ctrl_3_clk100m_reg
Logging control part automatic transfer mode (user circuit part)
re_rs_usr_wreg_095_clk100m_reg[0]
Always write register 14
re_rs_usr_alwreg_0e_clk100m_reg[1:0]
*1 E1 and E2 are connected in the same way.
*2 B1, B2, E0, E1, and E2 are connected in the same way.
*3 The following signals are connected.
A/D conversion value (E0): timd_ioe0_aival_0_clk100m_reg[15:0] to timd_ioe0_aival_b_clk100m_reg[15:0]
A/D conversion value (E1): timd_ioe1_aival_0_clk100m_reg[15:0] to timd_ioe1_aival_b_clk100m_reg[15:0]
A/D conversion value (E2): timd_ioe2_aival_0_clk100m_reg[15:0] to timd_ioe2_aival_b_clk100m_reg[15:0]
■Logging control part function list
Function
Time division
Enable selection
logging data
generation
Data latch
User sampling pulse
output
Logging data selector
Logging control part (uc3_log_top)
*3
timd_logdat_sel_clk100m_reg
Time division logging
data generator
(uc4_log_tim_divi_ctrl)
timd_divi_pulse_clk100m_1shot_reg
timd_divi_on_clk100m_reg
Description
It operates when "A/D conversion value enable (E0, E1, E2)" is selected from the "Logging control part user
sampling pulse signal selection" setting.
It receives the selected "A/D conversion value enable (E0, E1, E2)" and resets when the next logging control pulse
is received.
After reset, it outputs an enable signal to the level immediately below.
The A/D conversion value is latched by the signal output from enable selection.
Outputs the logging control pulse twice after receiving the pulse from the enable selection.
It generates a time division logging ON signal. When the user circuit logging mode selection [0]" is enabled (1) and
the upper/lower logging data is being logged, the time division logging ON signal becomes enabled (1).
The user circuit has the following two modes. Use "User circuit logging mode selection" to select a mode.
• Time division mode
Receives the sampling pulses that have been input, and outputs the logging data.
The first sampling pulse outputs [431:0] for logging.
The second sampling pulse outputs [943:512] for logging.
• Non-time division mode
Continues to output [431:0] regardless of timing.
Logging data
Logging data
uc_logdat_clk100m_reg[431:0]
selector
(uc4_log_datsel)
User sampling pulse
uc_loguserpulse_clk100m_reg
User sampling
pulse selector
[9:0]
(uc4_log_usrpulse)
Logging enable
uc_logen_clk100m_reg
[9:0]
Logging control violation flag: Rising edge
Logging enable
logctrl_uperr
selector
[0]
Logging control violation flag: Falling edge
(uc4_log_ensel)
logctrl_downerr
Logging end trigger
uc_logend_clk100m_reg
Logging end trigger
[9:0]
selector
(uc4_log_endsel)
[1]
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
271
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