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Logging control pulse
pls_tmgpulse_log_clk100m_1shot_reg
A/D conversion value enable (E0)
sim_ioe0_aival_vald_clk100m_reg
A/D conversion value enable (E1)
sim_ioe1_aival_vald_clk100m_reg
A/D conversion value enable (E2)
sim_ioe2_aival_vald_clk100m_reg
A/D conversion value 0...b (E0)
sim_ioe0_aival_0_clk100m_reg[15:0]...sim_ioe0_aival_b_clk100m_reg[15:0]
A/D conversion value 0...b (E1)
sim_ioe1_aival_0_clk100m_reg[15:0]...sim_ioe1_aival_b_clk100m_reg[15:0]
A/D conversion value 0...b (E2)
sim_ioe2_aival_0_clk100m_reg[15:0]...sim_ioe2_aival_b_clk100m_reg[15:0]
After fetch of A/D conversion value 0...b (E0)
After fetch of A/D conversion value 0...b (E1)
After fetch of A/D conversion value 0...b (E2)
Logging control part user sampling pulse signal selection
re_rs_usr_wreg_093_clk100m_reg[6:0]
A/D conversion value enable latch
sim_ioe_en_lat
Logging data (A/D conversion values (E0, E1, E2))
timd_ioex_aival_0_clk100m_reg[15:0]...timd_ioex_aival_b_clk100m_reg[15:0]
Lower side logging data select
log_sel_l_clk100m_reg
Upper side logging data select enable
log_sel_u_en_clk100m_reg
Upper side logging data select
log_sel_u_clk100m_reg
Logging data select
timd_logdat_sel_clk100m_reg
Time division enable pulse
timd_divi_pulse_clk100m_1shot_reg
Time division logging ON signal
timd_divi_on_front_clk100m_reg
Time division logging ON signal delay
timd_divi_on_front_delay_clk100m_reg
Time division logging ON signal
timd_divi_on_clk100m_reg
1μs
(I)
L
(I)
L
(I)
L
(I)
L
(I)
DATA0_0
DATA0_1
(I)
DATA1_0
DATA1_1
(I)
DATA2_0
DATA2_1
(Internal)
DATA0_0
DATA0_1
(Internal)
DATA1_0
DATA1_1
(Internal)
DATA2_0
DATA2_1
(I)
(Internal)
L
(O)
(Internal)
L
(Internal)
L
(Internal)
L
(O) L
(O)
L
(Internal)
L
(Internal)
L
(O) L
DATA0_2
DATA1_2
DATA2_2
DATA0_2
DATA1_2
DATA2_2
15H (extension circuit board 0 selected)
15H (extension circuit board 0 selected)
DATA0_1, DATA1_1, DATA2_1
42clk
42clk
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
DATA0_2, DATA1_2, DATA2_2
277
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Troubleshooting
