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■Loading A/D conversion value
The A/D conversion value is loaded at "A/D conversion value enable". The data corresponding to loading is shown below.
A/D conversion value enable
(loaded if (1))
sim_ioe0_aival_vald_clk100m_reg
sim_ioe1_aival_vald_clk100m_reg
sim_ioe2_aival_vald_clk100m_reg
■Generating logging data
Select an extension module (E0, E1, E2) targeted for logging timing, and generate logging data synchronized with "A/D
conversion value enable" of the selected extension module. For the extension module targeted for logging timing, select it
from "Logging control part user sampling pulse signal selection (re_rs_usr_wreg_093_clk100m_reg)". Latch (sim_ioe_en_lat)
it with enable signals of the selected "A/D conversion enable (sim_ioe0_aival_vald_clk100m_reg)", "A/D conversion enable
(sim_ioe1_aival_vald_clk100m_reg)", and "A/D conversion enable (sim_ioe2_aival_vald_clk100m_reg)". Generate the
following logging data from the latched enable signal and the periodically input "Logging control pulse
(pls_tmgpulse_log_clk100m_1shot_reg)".
timd_ioe0_aival_0_clk100m_reg, timd_ioe0_aival_b_clk100m_reg, timd_ioe1_aival_0_clk100m_reg,
timd_ioe1_aival_b_clk100m_reg, timd_ioe2_aival_0_clk100m_reg, timd_ioe2_aival_b_clk100m_reg
Target enable selection, target enable signal latch, and logging data generation are shown below.
• Target enable selection
Logging control part: User sampling pulse signal
selection
(re_rs_usr_wreg_093_clk100m_reg[6:0])
15h
16h
17h
Except for that shown above
• Target enable signal latch
usr_rst_n
clk100m
0b (enable)
1b (disable)
1b
• Generation of logging data
usr_rst_n
clk100m
0b (enable)
1b (disable)
1b
*1 E1 and E2 have the same structure.
11 FPGA INTERNAL CIRCUIT
278
11.4 User Circuit Block
A/D conversion value target signal
sim_ioe0_aival_0_clk100m_reg to
sim_ioe0_aival_b_clk100m_reg
sim_ioe1_aival_0_clk100m_reg to
sim_ioe1_aival_b_clk100m_reg
sim_ioe2_aival_0_clk100m_reg to
sim_ioe2_aival_b_clk100m_reg
Selection signal
Logging control pulse
(sim_ioe_en)
(pls_tmgpulse_log_clk100m
_1shot_reg)
1b
0b
1b
Select signal enable
Logging control pulse
signal latch
(pls_tmgpulse_log_clk100m
(sim_ioe_en_lat)
_1shot_reg)
0b (disable)
1b (enable)
1b
Signal after loading A/D conversion
value
sim_ioe0_aival_0_d1_clk100m_reg to
sim_ioe0_aival_b_d1_clk100m_reg
sim_ioe1_aival_0_d1_clk100m_reg to
sim_ioe1_aival_b_d1_clk100m_reg
sim_ioe2_aival_0_d1_clk100m_reg to
sim_ioe2_aival_b_d1_clk100m_reg
Selection signal (sim_ioe_en)
sim_ioe0_aival_vald_clk100m_reg
sim_ioe1_aival_vald_clk100m_reg
sim_ioe2_aival_vald_clk100m_reg
Fixed to 0.
Select signal enable signal latch
(sim_ioe_en_lat)
0b (enable)
1b (disable)
0b
A/D conversion value (E0)
(timd_ioe0_aival_0_clk100m_reg[15:0] to
timd_ioe0_aival_b_clk100m_reg[15:0])
Outputs all 0s.
Holds the previous value.
sim_ioe0_aival_0_d1_clk100m_reg to
sim_ioe0_aival_b_d1_clk100m_reg
Remarks
E0
E1
E2
Remarks
Select E0.
Select E1.
Select E2.
No selection
*1
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