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■Logging data select signal generation, time division enable pulse generation, time division
logging ON signal generation
Generates "Logging data select (timd_logdat_sel_clk100m_reg)" and "Time division enable pulse
(timd_divi_pulse_clk100m_1shot_reg)" that select the upper and lower A/D conversion values. The time division enable pulse
is output twice at "Logging control pulse receive (pls_tmgpulse_log_clk100m_1shot_reg)" after A/D conversion value is
loaded (sim_ioe_en_lat=1 (enabled)). For the output timing, refer to the timing chart. The logging data select is output by a
flip-flop that is set (selects the upper logging data) with the first time division enable pulse and reset (selects the lower logging
data) with its second time. Time division logging ON is generated by SR-FF, which is set at the first time division enable pulse
and reset at the second time, and the generated signal is expanded by 42 cycles and then output. For the output timing, refer
to the timing chart.
Logging data selector
Logging data is structured with various counters, counter control signals, and A/D conversion values. "User circuit logging
mode selection (re_rs_usr_logmode_sel_1_0_clk100m_reg[0])" selects whether to enable or disable time division.
When time division is enabled, the logging data is output alternately between upper and lower sections by logging data
selection. A block diagram of the logging data selector is shown below. For bit assignment of logging data, refer to the
following.
Page 714 Logging Data Bit Assignment
Digital input signals, various counters,
counter control signals
Various counters, counter control signals
Upper A/D conversion value
Lower A/D conversion value
Logging data select
timd_logdat_sel_clk100m_reg
User circuit logging mode selection
re_rs_usr_logmode_sel_1_0_clk100m_reg[0]
■Selector 0
Selects the logging data by "User circuit logging mode selection (re_rs_usr_logmode_sel_1_0_clk100m_reg[0])".
(Assignment of [431:0] of [1023:0] in time division mode)
User circuit logging mode
selection
0b
1b
Logging control part (uc3_log_top)
Logging data selector (uc4_log_datsel)
Selector 0
[271:0]
0b
[271:0]
[191:0]
1b
[271:192]
All 0
[431:0]
[383:0]
[432:384]
All 0
Bit assignment
{48{0b}, cnt_ioe2_32ring_2pha4multi_counter_clk100m_reg[31:0], 14{0b}, cnt_ioe2_32ring_2pha4multi_phb,
cnt_ioe2_32ring_2pha4multi_pha, cnt_ioe1_32ring_2pha4multi_counter_clk100m_reg[31:0], 14{0b},
cnt_ioe1_32ring_2pha4multi_phb, cnt_ioe1_32ring_2pha4multi_pha,
cnt_ioe0_32ring_2pha4multi_counter_clk100m_reg[31:0], 14{0b}, cnt_ioe0_32ring_2pha4multi_phb,
cnt_ioe0_32ring_2pha4multi_pha, cnt_iob2_32ring_2pha4multi_counter_clk100m_reg[31:0], 14{0b},
cnt_iob2_32ring_2pha4multi_phb, cnt_iob2_32ring_2pha4multi_pha,
cnt_iob1_32ring_2pha4multi_counter_clk100m_reg[31:0]}
{80{0b}, timd_ioe0_aival_b_clk100m_reg[15:0], timd_ioe0_aival_a_clk100m_reg[15:0],
timd_ioe0_aival_9_clk100m_reg[15:0], timd_ioe0_aival_8_clk100m_reg[15:0], timd_ioe0_aival_7_clk100m_reg[15:0],
timd_ioe0_aival_6_clk100m_reg[15:0], timd_ioe0_aival_5_clk100m_reg[15:0], timd_ioe0_aival_4_clk100m_reg[15:0],
timd_ioe0_aival_3_clk100m_reg[15:0], timd_ioe0_aival_2_clk100m_reg[15:0], timd_ioe0_aival_1_clk100m_reg[15:0],
timd_ioe0_aival_0_clk100m_reg[15:0]}
Selector 1
Selector 2
[431:0]
[159:0]
1b
0b
[431:0]
0b
1b
[431:160]
Logging data
D
Q
uc_logdat_clk100m_reg[431:0]
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
279
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Troubleshooting
