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User sampling pulse selector
The user sampling pulse selector outputs the user sampling pulse to the logging block. It selects "Digital input signal (B0 after
filtering)" and "Digital input signal (B0 after digital control)" from "Logging control part sampling pulse signal selection", and
selects "User sampling pulse" from "Logging control part sampling pulse signal selection". It outputs 1 pulse (clk100m) when
the rising edge of the selected signal is detected.
A block diagram of the user sampling pulse selector is shown below.
Digital input signal (B0 after filtering)
sim_iob0_x_clk100m_reg[9:0]
Digital output signal (B0 after digital control)
dig_iob0_y_clk100m_reg[9:0]
Time division enable pulse
timd_divi_pulse_clk100m_1shot_reg
Logging control part sampling pulse
signal selection
re_rs_usr_wreg_093_clk100m_reg[6:0]
■Select sampling pulses
The signal (logusrpulse_sel) to be output to the level immediately below is selected according to the value set in "Logging
control part sampling pulse signal selection (re_rs_usr_wreg_093_clk100m_reg[6:0])". After the rising edge of the selected
signal is detected, it is output to the level immediately below.
If the value of "Logging control part sampling pulse signal selection (re_rs_usr_wreg_093_clk100m_reg)" is 15H, 16H, or 17H,
"Time division enable pulse (timd_divi_pulse_clk100m_1shot_reg)" is selected. Otherwise, the logusrpulse_sel rising edge
detection signal is selected and output.
The signals to be selected are shown below.
Logging control part sampling pulse
signal selection
(re_rs_usr_wreg_093_clk100m_reg[6:0])
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
Except for that shown above
Logging control part (uc3_log_top)
User sampling pulse selector (uc4_log_usrpulse)
logusrpulse_sel
Rising
User
edge
sampling
detection
pulse
selection
logusrpulse_sel
sim_iob0_x_clk100m_reg[0]
sim_iob0_x_clk100m_reg[1]
sim_iob0_x_clk100m_reg[2]
sim_iob0_x_clk100m_reg[3]
sim_iob0_x_clk100m_reg[4]
sim_iob0_x_clk100m_reg[5]
sim_iob0_x_clk100m_reg[6]
sim_iob0_x_clk100m_reg[7]
sim_iob0_x_clk100m_reg[8]
sim_iob0_x_clk100m_reg[9]
dig_iob0_y_clk100m_reg[0]
dig_iob0_y_clk100m_reg[1]
dig_iob0_y_clk100m_reg[2]
dig_iob0_y_clk100m_reg[3]
dig_iob0_y_clk100m_reg[4]
dig_iob0_y_clk100m_reg[5]
dig_iob0_y_clk100m_reg[6]
dig_iob0_y_clk100m_reg[7]
dig_iob0_y_clk100m_reg[8]
dig_iob0_y_clk100m_reg[9]
0b
uc_logusrpulse_up
other
15H
D Q
16H
17H
Description
Digital input signal of IOB0_X[0] (B0 after filtering)
Digital input signal of IOB0_X[1] (B0 after filtering)
Digital input signal of IOB0_X[2] (B0 after filtering)
Digital input signal of IOB0_X[3] (B0 after filtering)
Digital input signal of IOB0_X[4] (B0 after filtering)
Digital input signal of IOB0_X[5] (B0 after filtering)
Digital input signal of IOB0_X[6] (B0 after filtering)
Digital input signal of IOB0_X[7] (B0 after filtering)
Digital input signal of IOB0_X[8] (B0 after filtering)
Digital input signal of IOB0_X[9] (B0 after filtering)
Digital output signal of IOB0_Y[0] (B0 after digital control)
Digital output signal of IOB0_Y[1] (B0 after digital control)
Digital output signal of IOB0_Y[2] (B0 after digital control)
Digital output signal of IOB0_Y[3] (B0 after digital control)
Digital output signal of IOB0_Y[4] (B0 after digital control)
Digital output signal of IOB0_Y[5] (B0 after digital control)
Digital output signal of IOB0_Y[6] (B0 after digital control)
Digital output signal of IOB0_Y[7] (B0 after digital control)
Digital output signal of IOB0_Y[8] (B0 after digital control)
Digital output signal of IOB0_Y[9] (B0 after digital control)
Fixed to 0.
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
User sampling pulse
uc_loguserpulse_clk100m_reg
287
11
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