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■A/D conversion value maximum/minimum hold
Holds the maximum and minimum values of A/D conversion values input from the extension module (E0, E1, E2). The
maximum initial value is set to 8000H and the minimum initial value is set to 7FFFH, and when "A/D conversion value enable"
is set to Enable (1), they are compared with the A/D conversion value and held.
A/D conversion value maximum/minimum: By enabling the update of current values, the maximum and minimum values are
updated to the current A/D conversion value. The comparison and held results are connected to the read data. The truth table
for the maximum and minimum values of A/D conversion value maximum/minimum hold is shown below.
• Truth table for holding maximum A/D conversion value
Ex.
Described in CH0 of E0. CH1 to CHB of E0 and CH0 to CHB of E1 and E2 have the same function.
usr_rst_n
clk100m
0b (enable)
X
1b (disable)
1b
1b
• Truth table for maintaining minimum A/D conversion value
Ex.
Described in CH0 of E0. CH1 to CHB of E0 and CH0 to CHB of E1 and E2 have the same function.
usr_rst_n
clk100m
0b (enable)
X
1b (disable)
1b
1b
The maximum and minimum analog values are displayed in the register for each circuit board according to the "Analog control
A/D conversion value maximum/minimum selection" setting. The circuit board to select is shown below.
re_rs_usr_wreg_1d8_clk100m_reg
00b
01b
10b
11b
■A/D conversion value enable status
Implements a flip-flop that sets the extension module (E0, E1, E2) when A/D conversion value is enabled, and resets it when
"Internal operation start/stop" is set to Stop (1). The set/reset signal is connected to the read data. The A/D conversion value
enable status truth table is shown below.
usr_rst_n
clk100m
0b (enable)
X
1b (disable)
1b
1b
11 FPGA INTERNAL CIRCUIT
294
11.4 User Circuit Block
re_rs_usr_wreg_1d9_clk100
m_reg
0b (enable)
1b (disable)
0b
re_rs_usr_wreg_1d9_clk100
m_reg
1b (enable)
0b (disable)
0b
ai_ioe_aival_0_max to ai_ioe_aival_b_max
ai_ioe0_aival_0_max_clk100m_reg to
ai_ioe0_aival_b_max_clk100m_reg
ai_ioe1_aival_0_max_clk100m_reg to
ai_ioe1_aival_b_max_clk100m_reg
ai_ioe2_aival_0_max_clk100m_reg to
ai_ioe2_aival_b_max_clk100m_reg
ai_ioe0_aival_0_max_clk100m_reg to
ai_ioe0_aival_b_max_clk100m_reg
ai_ioe0_aival_vald
ai_ioe1_aival_vald
_clk100m_reg
_clk100m_reg
X
X
1b (enable)
X
X
1b (enable)
X
X
ai_ioe0_aival_vald_clk100m_reg
X
ai_ioe0_aival_0_clk100m_reg>ai_ioe0_aival_0_
max_clk100m_reg
ai_ioe0_aival_0_clk100m_regai_ioe0_aival_0_
max_clk100m_reg
ai_ioe0_aival_vald_clk100m_reg
X
ai_ioe0_aival_0_clk100m_reg<ai_ioe0_aival_0_
min_clk100m_reg
ai_ioe0_aival_0_clk100m_regai_ioe0_aival_0_
min_clk100m_reg
ai_ioe_aival_0_min to ai_ioe_aival_b_min
ai_ioe0_aival_0_min_clk100m_reg to
ai_ioe0_aival_b_min_clk100m_reg
ai_ioe1_aival_0_min_clk100m_reg to
ai_ioe1_aival_b_min_clk100m_reg
ai_ioe2_aival_0_min_clk100m_reg to
ai_ioe2_aival_b_min_clk100m_reg
ai_ioe0_aival_0_min_clk100m_reg to
ai_ioe0_aival_b_min_clk100m_reg
ai_ioe2_aival_vald
_clk100m_reg
X
X
X
1b (enable)
ai_ioe0_aival_0_max_clk100
m_reg
8000H
ai_ioe0_aival_0_clk100m_reg
ai_ioe0_aival_0_clk100m_reg
ai_ioe0_aival_0_max_clk100m_reg
ai_ioe0_aival_0_min_clk100
m_reg
7FFFH
ai_ioe0_aival_0_clk100m_reg
ai_ioe0_aival_0_clk100m_reg
ai_ioe0_aival_0_min_clk100m_reg
usr_rreg_18e_clk100m_reg
[0]
[1]
0b
0b
1b
Previous value
held
Previous
1b
value held
Previous
Previous value
value held
held
[2]
0b
Previous
value held
Previous
value held
1b
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