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ADC and DAC conversions do not start at the same time as the standard circuit and user circuit. Setting
completion for ADC and DAC can be determined by checking b0 of Always write register 15 (usr_alwreg_0F)
(FPGA register address: 1000_A02EH) of the user circuit part.
Stopping FPGA control
FPGA control is stopped by turning off and on FPGA control stop request (RY1).
FPGA control stop request
(RY1)
FPGA controlling flag
(RX0)
Internal operation
ADC
DAC
FPGA internal
part
Logging
Implemented in FPGA module
Executed by the program.
12 FUNCTIONS
316
12.5 FPGA Control Function
ON
OFF
ON
Start
A/D conversion enable
D/A conversion enable
Logging in progress
OFF
Stop
A/D conversion disable
D/A conversion disable
Stop
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Troubleshooting
