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FPGA control continuation setting
■Address
Name
FPGA control continuation setting
■Description
Sets whether to stop or continue FPGA control when the data link with the CPU module and master station is broken during
FPGA module operation in CC-Link IE TSN communication mode.
b15
b14
b13
b12
0 (fixed)
(1) FPGA control
0: Stop (default)
1: Continue
This setting is ignored in standalone mode.
■Enabling the setting
When Parameter save request (RY2) is turned on and off, the setting is enabled.
DAC offset
■Address
Name
DAC offset CH0(E0)
DAC offset CH1(E0)
DAC offset CH0(E1)
DAC offset CH1(E1)
DAC offset CH0(E2)
DAC offset CH1(E2)
■Description
Sets the DAC offset. For details on the offset function, refer to the following.
Page 211 Analog output control part (ao2_top)
■Setting range
0H to FFFFH (default: 8000H)
■Enabling the setting
Enabled at the start of FPGA control.
b11
b10
b9
b8
Remote buffer memory address
04D4H
b7
b6
b5
b4
Remote buffer memory address
0601H
0605H
0609H
060DH
0611H
0615H
Appendix 3 Remote Buffer Memory
b3
b2
b1
b0
(1)
APPX
493
A
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Troubleshooting
