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FPGA
Register
register
name
address
1000_B1AAH
usr_wreg_0D5
1000_B1B6H
usr_wreg_0DB
1000_B1B8H
usr_wreg_0DC
1000_B1BAH
usr_wreg_0DD
1000_B1C6H
usr_wreg_0E3
1000_B1C8H
usr_wreg_0E4
1000_B1CAH
usr_wreg_0E5
1000_B1D6H
usr_wreg_0EB
1000_B1D8H
usr_wreg_0EC
1000_B1DAH
usr_wreg_0ED
1000_B1E6H
usr_wreg_0F3
1000_B1E8H
usr_wreg_0F4
1000_B1EAH
usr_wreg_0F5
1000_B1F6H
usr_wreg_0FB
1000_B1F8H
usr_wreg_0FC
1000_B1FAH
usr_wreg_0FD
1000_B220H
usr_wreg_110
1000_B222H
usr_wreg_111
1000_B224H
usr_wreg_112
1000_B226H
usr_wreg_113
1000_B22AH
usr_wreg_115
1000_B22CH
usr_wreg_116
1000_B22EH
usr_wreg_117
1000_B230H
usr_wreg_118
1000_B234H
usr_wreg_11A
1000_B236H
usr_wreg_11B
1000_B238H
usr_wreg_11C
1000_B23AH
usr_wreg_11D
1000_B23EH
usr_wreg_11F
1000_B240H
usr_wreg_120
1000_B242H
usr_wreg_121
1000_B244H
usr_wreg_122
1000_B248H
usr_wreg_124
1000_B24AH
usr_wreg_125
1000_B24CH
usr_wreg_126
1000_B24EH
usr_wreg_127
1000_B252H
usr_wreg_129
1000_B254H
usr_wreg_12A
1000_B256H
usr_wreg_12B
Description
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (B0)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (lower side) (B1)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (upper side) (B1)
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (B1)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (lower side) (B2)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (upper side) (B2)
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (B2)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (lower side) (E0)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (upper side) (E0)
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (E0)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (lower side) (E1)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (upper side) (E1)
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (E1)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (lower side) (E2)
Counter control part 32-bit ring counter (1-phase multiple of 1) counter upper limit
value (upper side) (E2)
Counter control part 32-bit ring counter (1-phase multiple of 1) input signal
selection (E2)
Pulse output part pulse width upper limit value (lower side) (B0)
Pulse output part pulse width upper limit value (upper side) (B0)
Pulse output part output pulse count upper limit value (lower side) (B0)
Pulse output part output pulse count upper limit value (upper side) (B0)
Pulse output part pulse width upper limit value (lower side) (B1)
Pulse output part pulse width upper limit value (upper side) (B1)
Pulse output part output pulse count upper limit value (lower side) (B1)
Pulse output part output pulse count upper limit value (upper side) (B1)
Pulse output part pulse width upper limit value (lower side) (B2)
Pulse output part pulse width upper limit value (upper side) (B2)
Pulse output part output pulse count upper limit value (lower side) (B2)
Pulse output part output pulse count upper limit value (upper side) (B2)
Pulse output part pulse width upper limit value (lower side) (E0)
Pulse output part pulse width upper limit value (upper side) (E0)
Pulse output part output pulse count upper limit value (lower side) (E0)
Pulse output part output pulse count upper limit value (upper side) (E0)
Pulse output part pulse width upper limit value (lower side) (E1)
Pulse output part pulse width upper limit value (upper side) (E1)
Pulse output part output pulse count upper limit value (lower side) (E1)
Pulse output part output pulse count upper limit value (upper side) (E1)
Pulse output part pulse width upper limit value (lower side) (E2)
Pulse output part pulse width upper limit value (upper side) (E2)
Pulse output part output pulse count upper limit value (lower side) (E2)
Type
Read
Write
Parameter/
Control
Parameter
Parameter
Parameter/
Control
Parameter
Parameter
Parameter/
Control
Parameter
Parameter
Parameter/
Control
Parameter
Parameter
Parameter/
Control
Parameter
Parameter
Parameter/
Control
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
APPX
513
Appendix 4 FPGA register
A
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Troubleshooting
