Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 535

Cc-link ie tsn fpga module

Table of Contents

Differential output HOLD/CLEAR

Differential output HOLD/CLEAR (B0) (oport_iob0y_holdclr)

Differential output HOLD/CLEAR (B1) (oport_iob1y_holdclr)

Differential output HOLD/CLEAR (B2) (oport_iob2y_holdclr)

Differential output HOLD/CLEAR (E0) (oport_ioe0y_holdclr)

Differential output HOLD/CLEAR (E1) (oport_ioe1y_holdclr)

Differential output HOLD/CLEAR (E2) (oport_ioe2y_holdclr)

■Description

Fix the logic of output signals (IOB0_Y0 to IOB0_Y7) to output signals (IOE2_Y0 to IOE2_Y7) when b0 of internal operation

start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is stopped (0).

• 2H, 3H: HOLD (previous value held)

• 1H: CLEAR (fixed to H)

• 0H: CLEAR (fixed to L)

■FPGA initial value

■Firmware initial value

■Reset cause

■Precautions and restrictions

• Changes to this register when b0 of internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is

stopped (0) are immediately reflected.

• External reset ON/OFF setting (ioport_set) (FPGA register address: 1000_0020H) is reset ON (0), the differential output

circuit outside the FPGA is reset. Therefore, the logic of the output signals (IOB0_Y0 to IOB0_Y7) set by the differential

output HOLD/CLEAR to the output signals (IOE2_Y0 to IOE2_Y7) after output signal selection (after selection by the

oport_ioe2y_osel register) is not output outside the module.

• When a DC I/O circuit board is connected to B, the settings are disabled.

• When a DC I/O circuit board or an analog I/O circuit board is connected to E, the settings are disabled.

FPGA register address

Appendix 4 FPGA register

Troubleshooting