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Differential output HOLD/CLEAR
■Address
Name
Differential output HOLD/CLEAR (IOB0_DIO485_O) (B0) (ioport_iob0y_holdclr)
Differential output HOLD/CLEAR (IOB1_DIO485_O) (B1) (ioport_iob1y_holdclr)
Differential output HOLD/CLEAR (IOB2_DIO485_O) (B2) (ioport_iob2y_holdclr)
Differential output HOLD/CLEAR (IOE0_DIO485_O) (E0) (ioport_ioe0y_holdclr)
Differential output HOLD/CLEAR (IOE1_DIO485_O) (E1) (ioport_ioe1y_holdclr)
Differential output HOLD/CLEAR (IOE2_DIO485_O) (E2) (ioport_ioe2y_holdclr)
■Description
When the internal operation start/stop (mode_ctrl2) is stopped (0), the logic of the output signal (IOB_DIO485_O) or the
output signal (IOE_DIO485_O) is fixed.
• 2H, 3H: HOLD (previous value held)
• 1H: CLEAR (fixed to H)
• 0H: CLEAR (fixed to L)
■FPGA initial value
1H
■Firmware initial value
1H
■Reset cause
Reset
■Precautions and restrictions
• Changes to this register when b0 of internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is
stopped (0) are immediately reflected.
• If the external reset ON/OFF setting (ioport_set) is reset ON (0), the differential output circuit outside the FPGA is reset.
Therefore, the logic of the output signals (IOB_Y0 to IOB_Y7) set by the differential output HOLD/CLEAR to the output
signals (IOB_Y0 to IOB_Y7) after output signal selection (after selection by the oport_iob0y_osel register), or output
signals (IOE_Y0 to IOE_Y7) to the output signals (IOE_Y0 to IOE_Y7) after output signal selection (after selection
by the oport_ioe0y_osel register) is not output outside the module.
• When a DC I/O circuit board is connected to B or E, the settings are disabled.
• When an analog I/O circuit board is connected to E, the settings are disabled.
APPX
538
Appendix 4 FPGA register
FPGA register address
1000_5040H
1000_5042H
1000_5044H
1000_5046H
1000_5048H
1000_504AH
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