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D/A conversion value selection
■Address
Name
D/A conversion value selection (aoport_da_data_sel)
■Description
Selects the D/A conversion value to output to DAC.
b15
b14
b13
0 (fixed)
(1) CH0 D/A conversion value setting selection (E0)
*1
• 1: User circuit output
• 0: Register setting value
(2) CH1 D/A conversion value setting selection (E0)
*1
• 1: User circuit output
• 0: Register setting value
(3) CH0 D/A conversion value setting selection (E1)
*1
• 1: User circuit output
• 0: Register setting value
(4) CH1 D/A conversion value setting selection (E1)
*1
• 1: User circuit output
• 0: Register setting value
(5) CH0 D/A conversion value setting selection (E2)
*1
• 1: User circuit output
• 0: Register setting value
(6) CH1 D/A conversion value setting selection (E2)
*1
• 1: User circuit output
• 0: Register setting value
*1 Select the D/A conversion value CH (E) (uc_ioe_andat_clk100m_reg) from the user circuit part.
*2 Select D/A conversion value CH (E) (aoport_dae__data) (FPGA register address: 1000_7100H to 1000_710AH).
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
• Changes to this register when b0 of internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is
stopped (0) are immediately reflected.
• When a DC I/O circuit board or Differential I/O circuit board is connected to E, the settings are disabled.
• Set CH0 and CH1 to the same setting value.
• If register setting value (0) is set, set the following for each circuit board.
Item
D/A conversion timing selection (aoport_da_cyc_sel)
DAC LDAC signal selection (aoport_da_ldac_sel)
• When setting the user circuit output (1), set the following for each circuit board.
Item
D/A conversion timing selection (aoport_da_cyc_sel)
DAC LDAC signal selection (aoport_da_ldac_sel)
APPX
546
Appendix 4 FPGA register
b12
b11
b10
*2
*2
*2
*2
*2
*2
b9
b8
b7
b6
Description
Data update timing
Fixed to Low
Description
User circuit output
User circuit output
FPGA register address
1000_7002H
b5
b4
b3
b2
(6)
(5)
(4)
(3)
b1
b0
(2)
(1)
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Troubleshooting
