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FPGA register details (logging part)
Logging operation control register
■Address
Name
Logging operation control register (lgdw_ctrl)
■Description
Configure and control the logging operation. The firmware controls.
b15
b14
b13
0 (fixed)
(9)
(1) Start logging
• 1: Start logging (write enabled)
• 0: Stop logging (write disabled)
(2) Suspend logging
• 1: Suspend (write disabled)
• 0: Operating (write enabled)
(3) Disable logging stop
• 1: Ignore stop by logging start operation
• 0: Can be stopped by logging start operation
(4) Logging control trigger
• 1: Rising for logging start allowed
• 0: Logging start falling edge enable
(5) Logging operation mode
• 1: Trigger operation mode
• 0: Storage operation mode
(6) Buffer operation in storage operation mode
• 1: Ring buffer operation
• 0: Linear buffer operation
*1 The trigger operation mode is always the ring buffer operation.
■FPGA initial value
0000H
■Firmware initial value
0000H
■Reset cause
Reset
■Precautions and restrictions
When b0 of the user circuit logging mode selection (usr_logmode_sel) (FPGA register address: 1000_A002H) is set to time
division mode (1), only the user circuit output (1) can be used for the sampling pulse selection and logging start control
selection.
APPX
550
Appendix 4 FPGA register
b12
b11
b10
b9
(8)
0
(7)
(6)
(fixed)
*2
b8
b7
b6
b5
(5)
0 (fixed)
(7) Automatic transfer mode (logging part)
• 1: Automatic transfer mode enabled
• 0: Automatic transfer mode disabled
(8) Select logging start control
• 1: Register setting value (RY3)
The b0 of the logging operation control register (lgdw_ctrl) (FPGA register
address: 1000_9000H) is operated from the remote output signal (RY3).
• 0: User circuit output
Select the logging enable (uc_logen_clk100m_reg) from the user circuit part.
(9) Select sampling pulses
• 1: User circuit output
Logging is performed with the user sampling pulse
(uc_loguserpulse_clk100m_reg) from the user circuit part.
• 0: Logging cycle timing
Logging is performed at the cycle set by the logging cycle timing (tim_log_cyc)
(FPGA register address: 1000_2200H).
FPGA register address
1000_9000H
b4
b3
b2
b1
(4)
(3)
(2)
b0
(1)
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Troubleshooting
