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Always write register 13
■Address
Name
Always write register 13 (usr_alwreg_0D)
■Description
Stores the value to be output to the user circuit, and the status for each synchronization cycle of the master station when using
the CC-Link IE TSN network synchronous communication function.
• 1: With synchronization signal
• 0: Without synchronization signal
b15
b14
b13
b12
(16)
(15)
(14)
(13)
(13) CC-Link IE TSN network
synchronization signal 12
(14) CC-Link IE TSN network
synchronization signal 13
(15) CC-Link IE TSN network
synchronization signal 14
(16) CC-Link IE TSN network
synchronization signal 15
■FPGA initial value
0000H
■Firmware initial value
0000H
■Reset cause
Reset
Always write register 14
■Address
Name
Always write register 14 (usr_alwreg_0E)
■Description
Stores the value to be output to the user circuit, and clears the rising/falling edge of the logging control violation flag.
b15
b14
b13
b12
(3)
(1) Logging control violation flag rising edge clear
• 1: Clear
(2) Logging control violation flag falling edge clear
• 1: Clear
(3) Read/write register for user circuit
■FPGA initial value
0000H
■Firmware initial value
0000H
■Reset cause
Reset
b11
b10
b9
b8
(12)
(11)
(10)
(9)
(9) CC-Link IE TSN network
synchronization signal 8
(10) CC-Link IE TSN network
synchronization signal 9
(11) CC-Link IE TSN network
synchronization signal 10
(12) CC-Link IE TSN network
synchronization signal 11
b11
b10
b9
b8
b7
b6
b5
b4
(8)
(7)
(6)
(5)
(5) CC-Link IE TSN network
synchronization signal 4
(6) CC-Link IE TSN network
synchronization signal 5
(7) CC-Link IE TSN network
synchronization signal 6
(8) CC-Link IE TSN network
synchronization signal 7
b7
b6
b5
b4
FPGA register address
1000_A02AH
b3
b2
b1
b0
(4)
(3)
(2)
(1)
(1) CC-Link IE TSN network
synchronization signal 0
(2) CC-Link IE TSN network
synchronization signal 1
(3) CC-Link IE TSN network
synchronization signal 2
(4) CC-Link IE TSN network
synchronization signal 3
FPGA register address
1000_A02CH
b3
b2
b1
b0
(2)
(1)
APPX
Appendix 4 FPGA register
A
561
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Troubleshooting
