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User circuit logging mode selection
■Address
Name
User circuit logging mode selection (usr_logmode_sel)
■Description
Sets the non-time division/time division mode (time division enabled/disabled).
• Non-time division mode (time division disabled): Logs 512-bit (1 record) data together with time information for each
sampling.
• Time division mode (time division enabled): Logs 1024-bit (2 records) data together with time information for each
sampling.
When logging the A/D conversion value using the time division mode (time division enabled) in the sample circuit, set one of
the following to the logging control part sampling pulse signal selection (usr_wreg_093) (FPGA register address:
1000_B126H) from the user circuit part parameter setting. Logging is performed at the set circuit board A/D conversion timing.
• 15H: A/D conversion value enable(E0)
• 16H: A/D conversion value enable(E1)
• 17H: A/D conversion value enable(E2)
b15
b14
b13
b12
0 (fixed)
(1) Time division enable/disable
• 1: Enable
• 0: Disable
(2) Reserve
The b1 is the firmware control area. FPGA operation does not change.
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
• When time division is enabled (1), set as follows.
Item
Select logging start control
Select sampling pulses
Logging data file storage type
b11
b10
b9
b8
b7
b6
b5
b4
Description
User circuit output
User circuit output
Binary file
FPGA register address
1000_A002H
b3
b2
b1
b0
(2)
(1)
APPX
565
Appendix 4 FPGA register
A
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Troubleshooting
