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Logging control part sampling pulse signal selection
■Address
Name
Logging control part sampling pulse signal selection (usr_wreg_093)
■Description
Selects the user sampling pulse signal of the logging control part.
b15
b14
b13
b12
0 (fixed)
• 17H: A/D conversion value
• 12H: Digital control part
enable (E2)
output signal (IOB0_X7 B0)
• 16H: A/D conversion value
• 11H: Digital control part
enable (E1)
output signal (IOB0_X6 B0)
• 15H: A/D conversion value
• 10H: Digital control part
enable (E0)
output signal (IOB0_X5 B0)
• 14H: Digital control part
• FH: Digital control part
output signal (IOB0_X9 B0)
output signal (IOB0_X4 B0)
• 13H: Digital control part
output signal (IOB0_X8 B0)
Digital input control part output signal: Digital input signal from the digital input control part (B0 after filtering)
Digital control part output signal: Digital output signal from the digital control part (B0 after digital control)
■FPGA initial value
00H
■Firmware initial value
00H
■Reset cause
Reset
■Precautions and restrictions
To select the analog I/O circuit board and log the A/D conversion value, enable (1) b0 of user circuit logging mode selection
(usr_logmode_sel) and set this register to 15H to 17H. If the A/D conversion value does not require logging, disable (0) b0 of
user circuit logging mode selection (usr_logmode_sel) and set this register to 1H to 14H. Otherwise, the data will not be
stored properly in DDR3L SDRAM.
b11
b10
b9
b8
• EH: Digital control part
output signal (IOB0_X3 B0)
• DH: Digital control part
output signal (IOB0_X2 B0)
• CH: Digital control part
output signal (IOB0_X1 B0)
• BH: Digital control part
output signal (IOB0_X0 B0)
• AH: Digital input control part
output signal (IOB0_X9 B0)
b7
b6
b5
b4
Sampling pulse signal selection
• 9H: Digital input control part
output signal (IOB0_X8 B0)
• 8H: Digital input control part
output signal (IOB0_X7 B0)
• 7H: Digital input control part
output signal (IOB0_X6 B0)
• 6H: Digital input control part
output signal (IOB0_X5 B0)
• 5H: Digital input control part
output signal (IOB0_X4 B0)
FPGA register address
1000_B126H
b3
b2
b1
b0
• 4H: Digital input control part
output signal (IOB0_X3 B0)
• 3H: Digital input control part
output signal (IOB0_X2 B0)
• 2H: Digital input control part
output signal (IOB0_X1 B0)
• 1H: Digital input control part
output signal (IOB0_X0 B0)
• 0H: Not selected
APPX
581
Appendix 4 FPGA register
A
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