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Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection
■Address
Name
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B0) (usr_wreg_0A5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B1) (usr_wreg_0AD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (B2) (usr_wreg_0B5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E0) (usr_wreg_0BD)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E1) (usr_wreg_0C5)
Counter control part 32-bit ring counter (2-phase multiple of 4) input signal selection (E2) (usr_wreg_0CD)
■Description
Sets the input signal of the 32-bit ring counter (2-phase multiple of 4).
b15
b14
b13
0 (fixed)
(4)
(3) Phase B input selection
• 12H to 1FH: Same as 0H
*1
• 11H: IO_DIO485_I
*1
• 10H: IO_X[7]chF
*1
• FH: IO_X[6]chE
*1
• EH: IO_X[5]chD
*1
• DH: IO_X[4]chC
*1
• CH: IO_X[3]chB
*1
• BH: IO_X[2]chA
*1
• AH: IO_X[1]ch9
*1
• 9H: IO_X[0]ch8
• 8H: IO_X[7]ch7 or IO_DI422[7]
• 7H: IO_X[6]ch6 or IO_DI422[6]
• 6H: IO_X[5]ch5 or IO_DI422[5]
• 5H: IO_X[4]ch4 or IO_DI422[4]
• 4H: IO_X[3]ch3 or IO_DI422[3]
• 3H: IO_X[2]ch2 or IO_DI422[2]
• 2H: IO_X[1]ch1 or IO_DI422[1]
• 1H: IO_X[0]ch0 or IO_DI422[0]
• 0H: Phase B register input (b13)
(4) Phase B register input
• 1: 1 input
• 0: 0 input
*1 : B0 to B2, E0 to E2
■FPGA initial value
0000H
■Firmware initial value
0000H
■Reset cause
Reset
APPX
584
Appendix 4 FPGA register
b12
b11
b10
b9
(3)
*1
*1
*1
*1
*1
*1
*1
*1
b8
b7
b6
b5
0 (fixed)
(2)
(1) Phase A input selection
• 12H to 1FH: Same as 0H
*1
• 11H: IO_DIO485_I
*1
• 10H: IO_X[7]chF
*1
• FH: IO_X[6]chE
*1
• EH: IO_X[5]chD
*1
• DH: IO_X[4]chC
*1
• CH: IO_X[3]chB
*1
• BH: IO_X[2]chA
*1
• AH: IO_X[1]ch9
*1
• 9H: IO_X[0]ch8
• 8H: IO_X[7]ch7 or IO_DI422[7]
• 7H: IO_X[6]ch6 or IO_DI422[6]
• 6H: IO_X[5]ch5 or IO_DI422[5]
• 5H: IO_X[4]ch4 or IO_DI422[4]
• 4H: IO_X[3]ch3 or IO_DI422[3]
• 3H: IO_X[2]ch2 or IO_DI422[2]
• 2H: IO_X[1]ch1 or IO_DI422[1]
• 1H: IO_X[0]ch0 or IO_DI422[0]
• 0H: Phase A register input (b5)
(2) phase A register input
• 1: 1 input
• 0: 0 input
FPGA register address
1000_B14AH
1000_B15AH
1000_B16AH
1000_B17AH
1000_B18AH
1000_B19AH
b4
b3
b2
b1
(1)
*1
*1
*1
*1
*1
*1
*1
*1
b0
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