Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 597

Cc-link ie tsn fpga module

Table of Contents

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B0) (usr_wreg_1A0)

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B1) (usr_wreg_1A3)

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (B2) (usr_wreg_1A6)

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (E0) (usr_wreg_1A9)

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (E1) (usr_wreg_1AC)

Counter control part 32-bit ring counter (1-phase multiple of 1) preset instruction (E2) (usr_wreg_1AF)

■Description

Enables or disables the preset of the 32-bit ring counter (1-phase multiple of 1).

(1) Presets the 32-bit ring counter (1-phase multiple of 1).

• 1: Preset enable

• 0: Preset disable

■FPGA initial value

■Firmware initial value

■Reset cause

FPGA register address

Appendix 4 FPGA register

Troubleshooting