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Connection destination
Block name
Instance
name
Timing
u_tg2_top
generator
FPGA external
top1
FPGA external
top1
FPGA external
top1
FPGA external
top1
FPGA external
top1
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
612
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
tg_05us_tmgpulse
0.5us sampling
_clk100m_1shot_r
pulse for user
eg
circuit
IOB0_UNIT
Module type (B0)
IOB1_UNIT
Module type (B1)
IOB2_UNIT
Module type (B2)
IOE_UNIT
Module type (E0,
E1, E2)
cpu_intpl_in
General-purpose
input (for future
extension)
re_rd_mode_ctrl2_
Internal operation
0_clk100m_reg
start/stop
re_rs_usr_alwreg_
Always write
00_clk100m_reg
register 0
re_rs_usr_alwreg_
Always write
01_clk100m_reg
register 1
re_rs_usr_alwreg_
Always write
02_clk100m_reg
register 2
re_rs_usr_alwreg_
Always write
03_clk100m_reg
register 3
re_rs_usr_alwreg_
Always write
04_clk100m_reg
register 4
re_rs_usr_alwreg_
Always write
05_clk100m_reg
register 5
re_rs_usr_alwreg_
Always write
06_clk100m_reg
register 6
re_rs_usr_alwreg_
Always write
07_clk100m_reg
register 7
re_rs_usr_alwreg_
Always write
08_clk100m_reg
register 8
re_rs_usr_alwreg_
Always write
09_clk100m_reg
register 9
re_rs_usr_alwreg_
Always write
0a_clk100m_reg
register 10
re_rs_usr_alwreg_
Always write
0b_clk100m_reg
register 11
re_rs_usr_alwreg_
Always write
0c_clk100m_reg
register 12
re_rs_usr_alwreg_
Always write
0d_clk100m_reg
register 13
re_rs_usr_alwreg_
Always write
0e_clk100m_reg
register 14
re_rs_usr_alwreg_
Always write
0f_clk100m_reg
register 15
re_rs_usr_wreg_0
Write data 0
00_clk100m_reg
re_rs_usr_wreg_0
Write data 1
01_clk100m_reg
re_rs_usr_wreg_0
Write data 2
02_clk100m_reg
re_rs_usr_wreg_0
Write data 3
03_clk100m_reg
re_rs_usr_wreg_0
Write data 4
04_clk100m_reg
re_rs_usr_wreg_0
Write data 5
05_clk100m_reg
Bit
Input/
Polarity
width
output
1
Input
H
4
Input
4
Input
4
Input
5
Input
3
Input
1
Input
H
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
Initial
1shot
Sync clock
value
Feq
0H
100MHz
0H
100MHz
0H
100MHz
0H
100MHz
00H
100MHz
7H
100MHz
0H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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